From: Andi Shyti <andi.shyti@xxxxxxxxx> With the new getparam/setparam api, engines are mapped to context. Use for_each_context_engine() to loop through existing engines. Suggested-by: Tvrtko Ursulin <tvrtko.ursulin@xxxxxxxxx> Signed-off-by: Andi Shyti <andi.shyti@xxxxxxxxx> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@xxxxxxxxx> --- Just some debug to get more data from CI. --- lib/igt_dummyload.c | 38 +++++++++++++++++++++++++------------- 1 file changed, 25 insertions(+), 13 deletions(-) diff --git a/lib/igt_dummyload.c b/lib/igt_dummyload.c index 47f6b92b424b..e7f3f480dc26 100644 --- a/lib/igt_dummyload.c +++ b/lib/igt_dummyload.c @@ -39,6 +39,7 @@ #include "ioctl_wrappers.h" #include "sw_sync.h" #include "igt_vgem.h" +#include "i915/gem_engine_topology.h" #include "i915/gem_mman.h" /** @@ -86,7 +87,7 @@ emit_recursive_batch(igt_spin_t *spin, struct drm_i915_gem_relocation_entry relocs[2], *r; struct drm_i915_gem_execbuffer2 *execbuf; struct drm_i915_gem_exec_object2 *obj; - unsigned int engines[16]; + unsigned int flags[GEM_MAX_ENGINES]; unsigned int nengine; int fence_fd = -1; uint32_t *batch, *batch_start; @@ -94,17 +95,33 @@ emit_recursive_batch(igt_spin_t *spin, nengine = 0; if (opts->engine == ALL_ENGINES) { - unsigned int engine; + struct intel_execution_engine2 *engine; - for_each_physical_engine(fd, engine) { + for_each_context_engine(fd, opts->ctx, engine) { if (opts->flags & IGT_SPIN_POLL_RUN && - !gem_can_store_dword(fd, engine)) + !gem_class_can_store_dword(fd, engine->class)) continue; - engines[nengine++] = engine; + igt_debug("%u=%llx (%u:%u)\n", + nengine, + engine->flags, engine->class, engine->instance); + flags[nengine++] = engine->flags; } } else { - engines[nengine++] = opts->engine; + struct intel_execution_engine2 *e; + int class; + + if (!gem_ctx_get_engine(fd, opts->engine, opts->ctx, e)) { + class = e->class; + } else { + gem_require_ring(fd, opts->engine); + class = gem_eb_to_class(opts->engine); + } + + if (opts->flags & IGT_SPIN_POLL_RUN) + igt_require(gem_class_can_store_dword(fd, class)); + + flags[nengine++] = opts->engine; } igt_require(nengine); @@ -234,8 +251,9 @@ emit_recursive_batch(igt_spin_t *spin, for (i = 0; i < nengine; i++) { execbuf->flags &= ~ENGINE_MASK; - execbuf->flags |= engines[i]; + execbuf->flags |= flags[i]; + igt_debug("eb %u = %llx\n", i, flags[i]); gem_execbuf_wr(fd, execbuf); if (opts->flags & IGT_SPIN_FENCE_OUT) { @@ -308,12 +326,6 @@ igt_spin_batch_factory(int fd, const struct igt_spin_factory *opts) igt_require_gem(fd); - if (opts->engine != ALL_ENGINES) { - gem_require_ring(fd, opts->engine); - if (opts->flags & IGT_SPIN_POLL_RUN) - igt_require(gem_can_store_dword(fd, opts->engine)); - } - spin = spin_batch_create(fd, opts); igt_assert(gem_bo_busy(fd, spin->handle)); -- 2.19.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx