From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Write some icl pll calculations in a more straightforward way.
We have just enough bits for the full divisor.
Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
---
drivers/gpu/drm/i915/intel_ddi.c | 15 ++++-----------
drivers/gpu/drm/i915/intel_dpll_mgr.c | 2 +-
2 files changed, 5 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 720de7a3f5e6..0a24608ce49b 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1386,8 +1386,7 @@ static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
static int icl_calc_mg_pll_link(struct drm_i915_private *dev_priv,
const struct intel_dpll_hw_state *pll_state)
{
- u32 m1, m2_int, m2_frac, div1, div2, ref_clock;
- u64 tmp;
+ u32 m1, m2, m2_int, m2_frac, div1, div2, ref_clock;
ref_clock = dev_priv->cdclk.hw.ref;
@@ -1396,6 +1395,7 @@ static int icl_calc_mg_pll_link(struct drm_i915_private *dev_priv,
m2_frac = (pll_state->mg_pll_div0 & MG_PLL_DIV0_FRACNEN_H) ?
(pll_state->mg_pll_div0 & MG_PLL_DIV0_FBDIV_FRAC_MASK) >>
MG_PLL_DIV0_FBDIV_FRAC_SHIFT : 0;
+ m2 = (m2_int << 22) | m2_frac;
switch (pll_state->mg_clktop2_hsclkctl &
MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK) {
@@ -1424,15 +1424,8 @@ static int icl_calc_mg_pll_link(struct drm_i915_private *dev_priv,
if (div2 == 0)
div2 = 1;
- /*
- * Adjust the original formula to delay the division by 2^22 in order to
- * minimize possible rounding errors.
- */
- tmp = (u64)m1 * m2_int * ref_clock +
- (((u64)m1 * m2_frac * ref_clock) >> 22);
- tmp = div_u64(tmp, 5 * div1 * div2);
-
- return tmp;
+ return div_u64(mul_u32_u32(ref_clock * m1, m2),
+ (5 * div1 * div2) << 22);
}
static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 29edc369920b..3098c783a615 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -2682,7 +2682,7 @@ static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state)
}
m2div_rem = dco_khz % (refclk_khz * m1div);
- tmp = (u64)m2div_rem * (1 << 22);
+ tmp = (u64)m2div_rem << 22;
do_div(tmp, refclk_khz * m1div);
m2div_frac = tmp;
--
2.21.0
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