From: Kiran Kumar S <kiran.s.kumar@xxxxxxxxxxxxxxxxxxxxxxxxxxxxx>
As per the display workaround #1200, FBC needs wait for vblank before
enabling and before disabling FBC.
In some cases, depending on whether FBC was compressing in that frame,
several control signals in the compression engine also will fail to properly
recognize the final segment of the frame as a result of the missing last
pixel indication. As a result of this, we're seeing corrupted cache
line/compression indicators after FBC re-enables which causes underruns or
corruption when they're used to decompress.
WA sequence as below:
1) Display enables plane 1A
2) Wait for 1 vblank
3) FBC gets enabled
4) Wait for 1 VBLANK
5) Turn off FBC
In GLK Chrome OS, if FBC is enabled by default, few top lines on the screen
got corrupted. With the above WA, issue was resolved.
Change-Id: I6c5cc8978bc23fb6fc1f5fedd9599c6281bd78e9
Signed-off-by: Kiran Kumar S <kiran.s.kumar@xxxxxxxxxxxxxxxxxxxxxxxxxxxxx>
---
drivers/gpu/drm/i915/intel_display.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index c2d8589a4150..fec06447ab72 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12246,6 +12246,8 @@ static void intel_update_crtc(struct drm_crtc *crtc,
}
if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
+ /* Display WA #1200: GLK */
+ intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
intel_fbc_enable(
intel_crtc, pipe_config,
to_intel_plane_state(crtc->primary->state));
@@ -12419,6 +12421,8 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state)
intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state);
intel_crtc->active = false;
+ /* Display WA #1200: GLK */
+ intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
intel_fbc_disable(intel_crtc);
intel_disable_shared_dpll(intel_crtc);
--
2.7.4
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