On Fri, Mar 29, 2019 at 09:19:00AM -0700, Daniele Ceraolo Spurio wrote: > Those functions are used on gen4 as well and gen4 does have a non-RCS > engine, so remove the BUG_ON and flip back the logic to what it was > before the ENGINE_READ/WRITE update > > Fixes: baba6e572b38 ("drm/i915: take a reference to uncore in the engine and use it") > Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@xxxxxxxxx> > Cc: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> > Cc: Paulo Zanoni <paulo.r.zanoni@xxxxxxxxx> > --- > drivers/gpu/drm/i915/intel_ringbuffer.c | 10 +++------- > drivers/gpu/drm/i915/intel_ringbuffer.h | 1 + > 2 files changed, 4 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c > index 48ba4d61a4ae..586e75c9edf3 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -976,20 +976,16 @@ gen5_irq_disable(struct intel_engine_cs *engine) > static void > i9xx_irq_enable(struct intel_engine_cs *engine) > { > - GEM_BUG_ON(engine->id != RCS0); > - > engine->i915->irq_mask &= ~engine->irq_enable_mask; > - ENGINE_WRITE(engine, RING_IMR, engine->i915->irq_mask); > - ENGINE_POSTING_READ(engine, RING_IMR); > + intel_uncore_write(engine->uncore, IMR, engine->i915->irq_mask); > + ENGINE_POSTING_READ_FW(engine, RING_IMR); RING_IMR seems wrong still. > } > > static void > i9xx_irq_disable(struct intel_engine_cs *engine) > { > - GEM_BUG_ON(engine->id != RCS0); > - > engine->i915->irq_mask |= engine->irq_enable_mask; > - ENGINE_WRITE(engine, RING_IMR, engine->i915->irq_mask); > + intel_uncore_write(engine->uncore, IMR, engine->i915->irq_mask); > } > > static void > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h > index e58d6f04177b..f34459ffaeb8 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.h > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h > @@ -52,6 +52,7 @@ struct drm_printer; > #define ENGINE_READ(...) __ENGINE_READ_OP(read, __VA_ARGS__) > #define ENGINE_READ_FW(...) __ENGINE_READ_OP(read_fw, __VA_ARGS__) > #define ENGINE_POSTING_READ(...) __ENGINE_READ_OP(posting_read, __VA_ARGS__) > +#define ENGINE_POSTING_READ_FW(...) __ENGINE_READ_OP(posting_read_fw, __VA_ARGS__) > > #define ENGINE_READ64(engine__, lower_reg__, upper_reg__) \ > __ENGINE_REG_OP(read64_2x32, (engine__), \ > -- > 2.20.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrjälä Intel _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx