>-----Original Message----- >From: Ville Syrjälä [mailto:ville.syrjala@xxxxxxxxxxxxxxx] >Sent: Friday, March 29, 2019 6:41 PM >To: Shankar, Uma <uma.shankar@xxxxxxxxx> >Cc: intel-gfx@xxxxxxxxxxxxxxxxxxxxx; Syrjala, Ville <ville.syrjala@xxxxxxxxx>; Lankhorst, >Maarten <maarten.lankhorst@xxxxxxxxx> >Subject: Re: [PATCH 2/2] drm/i915: Program EXT2 GC MAX registers > >On Fri, Mar 29, 2019 at 06:19:19PM +0530, Uma Shankar wrote: >> EXT2 GC MAX registers are introduced from Gen10+ to program values >> from 3.0 to 7.0. Enabled the same, but currently limiting it to 1.0 as >> userspace ABI is limited at that currently. >> >> Signed-off-by: Uma Shankar <uma.shankar@xxxxxxxxx> >> --- >> drivers/gpu/drm/i915/i915_reg.h | 1 + >> drivers/gpu/drm/i915/intel_color.c | 28 ++++++++++++++++++++++++++++ >> 2 files changed, 29 insertions(+) >> >> diff --git a/drivers/gpu/drm/i915/i915_reg.h >> b/drivers/gpu/drm/i915/i915_reg.h index c866379..341f03e 100644 >> --- a/drivers/gpu/drm/i915/i915_reg.h >> +++ b/drivers/gpu/drm/i915/i915_reg.h >> @@ -10144,6 +10144,7 @@ enum skl_power_gate { >> #define PREC_PAL_DATA(pipe) _MMIO_PIPE(pipe, >_PAL_PREC_DATA_A, _PAL_PREC_DATA_B) >> #define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, >_PAL_PREC_GC_MAX_B) + (i) * 4) >> #define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, >_PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4) >> +#define PREC_PAL_EXT2_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, >_PAL_PREC_EXT2_GC_MAX_A, _PAL_PREC_EXT2_GC_MAX_B) + (i) * 4) >> >> #define _PRE_CSC_GAMC_INDEX_A 0x4A484 >> #define _PRE_CSC_GAMC_INDEX_B 0x4AC84 >> diff --git a/drivers/gpu/drm/i915/intel_color.c >> b/drivers/gpu/drm/i915/intel_color.c >> index dd179a8..84aa5e7 100644 >> --- a/drivers/gpu/drm/i915/intel_color.c >> +++ b/drivers/gpu/drm/i915/intel_color.c >> @@ -526,6 +526,20 @@ static void bdw_load_gamma_lut(const struct >intel_crtc_state *crtc_state, u32 of >> I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 0), (1 << 16) - 1); >> I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 1), (1 << 16) - 1); >> I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 2), (1 << 16) - 1); >> + >> + /* >> + * Program the gc max 2 register to clamp values > 1.0. >> + * ToDo: Extend the ABI to be able to program values >> + * from 3.0 to 7.0 >> + */ >> + if (INTEL_GEN(dev_priv) >= 10) { > >|| IS_GEMINILAKE Yeah, GLK needs to be added here. Will update it. >> + I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 0), >> + (1 << 16) - 1); >> + I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 1), >> + (1 << 16) - 1); >> + I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 2), >> + (1 << 16) - 1); >> + } >> } else { >> for (i = 0; i < lut_size; i++) { >> u32 v = (i * ((1 << 10) - 1)) / (lut_size - 1); @@ -537,6 +551,20 >> @@ static void bdw_load_gamma_lut(const struct intel_crtc_state *crtc_state, u32 >of >> I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 0), (1 << 16) - 1); >> I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 1), (1 << 16) - 1); >> I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 2), (1 << 16) - 1); >> + >> + /* >> + * Program the gc max 2 register to clamp values > 1.0. >> + * ToDo: Extend the ABI to be able to program values >> + * from 3.0 to 7.0 >> + */ >> + if (INTEL_GEN(dev_priv) >= 10) { > >same > >> + I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 0), >> + (1 << 16) - 1); >> + I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 1), >> + (1 << 16) - 1); >> + I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 2), >> + (1 << 16) - 1); >> + } >> } >> >> /* >> -- >> 1.9.1 >> >> _______________________________________________ >> Intel-gfx mailing list >> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx > >-- >Ville Syrjälä >Intel _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
