On Fri, 08 Mar 2019, Ville Syrjala <ville.syrjala@xxxxxxxxxxxxxxx> wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> Update the DP MSA MISC bits for fastsets. This is needed
> when we change between limited and full range RGB output.
>
> On HSW+ changing limited_range does not currently result in a
> full modeset since we have don't have the readout code for it
> (for DP we could, and probably should, readout from TRANS_MSA_MISC
> itself, for HDMI we would have to rely on the infoframe). So
> the PIPE_CONF_CHECK() is only performed for pre-HSW platforms.
> That means any change in the value will result in a fastset
> instead. Fortunately there is no prohibition to changing
> TRANS_MSA_MISC dynamically, so it looks like we can legally do
> fastsets for this.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Reviewed-by: Jani Nikula <jani.nikula@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 7e3b4e8fdf3a..3d9ad4526cf9 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -3556,6 +3556,8 @@ static void intel_ddi_update_pipe_dp(struct intel_encoder *encoder,
> {
> struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
>
> + intel_ddi_set_pipe_settings(crtc_state);
> +
> intel_psr_update(intel_dp, crtc_state);
> intel_edp_drrs_enable(intel_dp, crtc_state);
--
Jani Nikula, Intel Open Source Graphics Center
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