✗ Fi.CI.CHECKPATCH: warning for series starting with [1/8] drm/i915/psr: Remove partial PSR support on multiple transcoders

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== Series Details ==

Series: series starting with [1/8] drm/i915/psr: Remove partial PSR support on multiple transcoders
URL   : https://patchwork.freedesktop.org/series/58373/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
95c7ad172d42 drm/i915/psr: Remove partial PSR support on multiple transcoders
32e9f40119c2 drm/i915: Move PSR mmio base to PSR struct
-:62: WARNING:LONG_LINE_COMMENT: line over 100 characters
#62: FILE: drivers/gpu/drm/i915/i915_reg.h:4291:
+#define EDP_PSR_AUX_DATA(i)			_MMIO(dev_priv->psr.mmio_base + 0x14 + (i) * 4) /* 5 registers */

-:78: WARNING:LONG_LINE_COMMENT: line over 100 characters
#78: FILE: drivers/gpu/drm/i915/i915_reg.h:4321:
+#define EDP_PSR_DEBUG				_MMIO(dev_priv->psr.mmio_base + 0x60) /* PSR_MASK on SKL+ */

total: 0 errors, 2 warnings, 0 checks, 62 lines checked
f40f1d840cae drm/i915/psr: Make all PSR register relative to mmio base
32905478ea42 drm/i915/psr: Make mmio base relative to transcoder offset
-:75: WARNING:LONG_LINE_COMMENT: line over 100 characters
#75: FILE: drivers/gpu/drm/i915/i915_reg.h:4290:
+#define EDP_PSR_AUX_DATA(i)			_MMIO(dev_priv->psr.mmio_base + 0x814 + (i) * 4) /* 5 registers */

-:91: WARNING:LONG_LINE_COMMENT: line over 100 characters
#91: FILE: drivers/gpu/drm/i915/i915_reg.h:4320:
+#define EDP_PSR_DEBUG				_MMIO(dev_priv->psr.mmio_base + 0x860) /* PSR_MASK on SKL+ */

-:140: WARNING:LONG_LINE: line over 100 characters
#140: FILE: drivers/gpu/drm/i915/intel_psr.c:679:
+		dev_priv->psr.mmio_base = INTEL_INFO(dev_priv)->trans_offsets[dev_priv->psr.transcoder];

total: 0 errors, 3 warnings, 0 checks, 106 lines checked
9cf701d3e3ac drm/i915/psr: Initialize PSR mutex even when sink is not reliable
79f515d2066b drm/i915/psr: Do not enable PSR in interlaced mode for all GENs
e2bfa61adcf5 drm/i915: Remove unused VLV/CHV PSR registers
cf712ab15a65 drm/i915/bdw+: Move misc display IRQ handling to it own function

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