On Tue, 19 Mar 2019, Manasi Navare <manasi.d.navare@xxxxxxxxx> wrote:
> This patch fixes the PORT_SYNC_MODE_MASTER_SELECT macro
> to correctly do the left shifting to set the port sync
> master select correctly.
> I have tested this fix on ICL.
>
> Fixes: 49edbd49786e ("drm/i915/icl: Define TRANS_DDI_FUNC_CTL DSI registers")
> Cc: Madhav Chauhan <madhav.chauhan@xxxxxxxxx>
> Cc: Jani Nikula <jani.nikula@xxxxxxxxx>
> Signed-off-by: Manasi Navare <manasi.d.navare@xxxxxxxxx>
Auch.
Reviewed-by: Jani Nikula <jani.nikula@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 85e8d1a1f70b..7a9d867eb49b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9352,7 +9352,7 @@ enum skl_power_gate {
> #define TRANS_DDI_FUNC_CTL2(tran) _MMIO_TRANS2(tran, \
> _TRANS_DDI_FUNC_CTL2_A)
> #define PORT_SYNC_MODE_ENABLE (1 << 4)
> -#define PORT_SYNC_MODE_MASTER_SELECT(x) ((x) < 0)
> +#define PORT_SYNC_MODE_MASTER_SELECT(x) ((x) << 0)
> #define PORT_SYNC_MODE_MASTER_SELECT_MASK (0x7 << 0)
> #define PORT_SYNC_MODE_MASTER_SELECT_SHIFT 0
--
Jani Nikula, Intel Open Source Graphics Center
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