On Tue, Mar 12, 2019 at 10:58:39PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> Currently we just assume that 32 or 8 blocks of ddb is sufficient
> for the cursor. The 32 might be, but the 8 is certainly not. The
> minimum we need is at least what level 0 watermarks need, but that
> is a bit restrictive, so instead let's calculate what level 7
> would need for a 256x256 cursor. We'll use that to determine the
> fixed ddb allocation for the cursor. This way the cursor will never
> be responsible for missing out on deeper power saving states.
>
> Cc: Neel Desai <neel.desai@xxxxxxxxx>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 33 ++++++++++++++++++++++++++++-----
> 1 file changed, 28 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 9e7b4412f7a8..ae9a0ce4dcb9 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3924,12 +3924,35 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
> alloc->end = ddb_size * (width_before_pipe + pipe_width) / total_width;
> }
>
> -static unsigned int skl_cursor_allocation(int num_active)
> +static int skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
> + int width, const struct drm_format_info *format,
> + u64 modifier, unsigned int rotation,
> + u32 plane_pixel_rate, struct skl_wm_params *wp,
> + int color_plane);
> +static void skl_compute_plane_wm(const struct intel_crtc_state *cstate,
> + int level,
> + const struct skl_wm_params *wp,
> + const struct skl_wm_level *result_prev,
> + struct skl_wm_level *result /* out */);
> +
> +static unsigned int
> +skl_cursor_allocation(const struct intel_crtc_state *crtc_state,
> + int num_active)
> {
> - if (num_active == 1)
> - return 32;
> + struct skl_wm_level wm = {};
> + struct skl_wm_params wp;
> + int ret;
> +
> + ret = skl_compute_wm_params(crtc_state, 256,
> + drm_format_info(DRM_FORMAT_ARGB8888),
> + DRM_FORMAT_MOD_LINEAR,
> + DRM_MODE_ROTATE_0,
> + crtc_state->pixel_rate, &wp, 0);
> + WARN_ON(ret);
> +
> + skl_compute_plane_wm(crtc_state, 7, &wp, &wm, &wm);
Hmm. This borked if latency[7]==0. I guess I actually need to loop
here...
>
> - return 8;
> + return max_t(int, num_active == 1 ? 32 : 8, wm.min_ddb_alloc);
> }
>
> static void skl_ddb_entry_init_from_hw(struct drm_i915_private *dev_priv,
> @@ -4354,7 +4377,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
> return 0;
>
> /* Allocate fixed number of blocks for cursor. */
> - total[PLANE_CURSOR] = skl_cursor_allocation(num_active);
> + total[PLANE_CURSOR] = skl_cursor_allocation(cstate, num_active);
> alloc_size -= total[PLANE_CURSOR];
> cstate->wm.skl.plane_ddb_y[PLANE_CURSOR].start =
> alloc->end - total[PLANE_CURSOR];
> --
> 2.19.2
--
Ville Syrjälä
Intel
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