Em qua, 2019-03-13 às 16:13 -0700, Daniele Ceraolo Spurio escreveu:
> Now that the internal code all works on intel_uncore, flip the
> external-facing interface.
Long but trivial patch. It breaks compilation of gvt but that's also
trivial to fix.
Unlike patches 1 and 2, this one doesn't add much value on its own IMHO
(i.e., without the rest of the series), but it still helps intel_uncore
move away from the God Object pattern of dev_priv. I'll add my r-b to
the version with the gvt fix when it's sent.
>
> Cc: Paulo Zanoni <paulo.r.zanoni@xxxxxxxxx>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/gvt/mmio_context.c | 8 +--
> drivers/gpu/drm/i915/i915_debugfs.c | 12 ++---
> drivers/gpu/drm/i915/i915_gem.c | 20 +++----
> drivers/gpu/drm/i915/i915_perf.c | 6 +--
> drivers/gpu/drm/i915/i915_reset.c | 12 ++---
> drivers/gpu/drm/i915/intel_display.c | 4 +-
> drivers/gpu/drm/i915/intel_engine_cs.c | 4 +-
> drivers/gpu/drm/i915/intel_guc.c | 8 +--
> drivers/gpu/drm/i915/intel_guc_fw.c | 4 +-
> drivers/gpu/drm/i915/intel_huc_fw.c | 4 +-
> drivers/gpu/drm/i915/intel_pm.c | 52 +++++++++----------
> drivers/gpu/drm/i915/intel_ringbuffer.c | 8 +--
> drivers/gpu/drm/i915/intel_uncore.c | 50 ++++++++----------
> drivers/gpu/drm/i915/intel_uncore.h | 12 ++---
> drivers/gpu/drm/i915/intel_workarounds.c | 4 +-
> drivers/gpu/drm/i915/selftests/intel_uncore.c | 4 +-
> 16 files changed, 102 insertions(+), 110 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c
> index f64c76dd11d4..a00a807a1d55 100644
> --- a/drivers/gpu/drm/i915/gvt/mmio_context.c
> +++ b/drivers/gpu/drm/i915/gvt/mmio_context.c
> @@ -356,7 +356,7 @@ static void handle_tlb_pending_event(struct intel_vgpu *vgpu, int ring_id)
> if (ring_id == RCS0 && INTEL_GEN(dev_priv) >= 9)
> fw |= FORCEWAKE_RENDER;
>
> - intel_uncore_forcewake_get(dev_priv, fw);
> + intel_uncore_forcewake_get(&dev_priv->uncore, fw);
>
> I915_WRITE_FW(reg, 0x1);
>
> @@ -365,7 +365,7 @@ static void handle_tlb_pending_event(struct intel_vgpu *vgpu, int ring_id)
> else
> vgpu_vreg_t(vgpu, reg) = 0;
>
> - intel_uncore_forcewake_put(dev_priv, fw);
> + intel_uncore_forcewake_put(&dev_priv->uncore, fw);
>
> gvt_dbg_core("invalidate TLB for ring %d\n", ring_id);
> }
> @@ -552,9 +552,9 @@ void intel_gvt_switch_mmio(struct intel_vgpu *pre,
> * performace for batch mmio read/write, so we need
> * handle forcewake mannually.
> */
> - intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
> switch_mmio(pre, next, ring_id);
> - intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
> }
>
> /**
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 3bcf0e07b614..0c037bbcf4c8 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1094,7 +1094,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
> }
>
> /* RPSTAT1 is in the GT power well */
> - intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
>
> reqf = I915_READ(GEN6_RPNSWREQ);
> if (INTEL_GEN(dev_priv) >= 9)
> @@ -1122,7 +1122,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
> cagf = intel_gpu_freq(dev_priv,
> intel_get_cagf(dev_priv, rpstat));
>
> - intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
>
> if (INTEL_GEN(dev_priv) >= 11) {
> pm_ier = I915_READ(GEN11_GPM_WGBOXPERF_INTR_ENABLE);
> @@ -2060,12 +2060,12 @@ static int i915_rps_boost_info(struct seq_file *m, void *data)
> u32 rpup, rpupei;
> u32 rpdown, rpdownei;
>
> - intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
> rpup = I915_READ_FW(GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK;
> rpupei = I915_READ_FW(GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK;
> rpdown = I915_READ_FW(GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK;
> rpdownei = I915_READ_FW(GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK;
> - intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
>
> seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n",
> rps_power_to_str(rps->power.mode));
> @@ -4255,7 +4255,7 @@ static int i915_forcewake_open(struct inode *inode, struct file *file)
> return 0;
>
> file->private_data = (void *)(uintptr_t)intel_runtime_pm_get(i915);
> - intel_uncore_forcewake_user_get(i915);
> + intel_uncore_forcewake_user_get(&i915->uncore);
>
> return 0;
> }
> @@ -4267,7 +4267,7 @@ static int i915_forcewake_release(struct inode *inode, struct file *file)
> if (INTEL_GEN(i915) < 6)
> return 0;
>
> - intel_uncore_forcewake_user_put(i915);
> + intel_uncore_forcewake_user_put(&i915->uncore);
> intel_runtime_pm_put(i915,
> (intel_wakeref_t)(uintptr_t)file->private_data);
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index b38c9531b5e8..2cff3f3061b8 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -4315,7 +4315,7 @@ void i915_gem_sanitize(struct drm_i915_private *i915)
> GEM_TRACE("\n");
>
> wakeref = intel_runtime_pm_get(i915);
> - intel_uncore_forcewake_get(i915, FORCEWAKE_ALL);
> + intel_uncore_forcewake_get(&i915->uncore, FORCEWAKE_ALL);
>
> /*
> * As we have just resumed the machine and woken the device up from
> @@ -4336,7 +4336,7 @@ void i915_gem_sanitize(struct drm_i915_private *i915)
> */
> intel_engines_sanitize(i915, false);
>
> - intel_uncore_forcewake_put(i915, FORCEWAKE_ALL);
> + intel_uncore_forcewake_put(&i915->uncore, FORCEWAKE_ALL);
> intel_runtime_pm_put(i915, wakeref);
>
> mutex_lock(&i915->drm.struct_mutex);
> @@ -4435,7 +4435,7 @@ void i915_gem_resume(struct drm_i915_private *i915)
> WARN_ON(i915->gt.awake);
>
> mutex_lock(&i915->drm.struct_mutex);
> - intel_uncore_forcewake_get(i915, FORCEWAKE_ALL);
> + intel_uncore_forcewake_get(&i915->uncore, FORCEWAKE_ALL);
>
> i915_gem_restore_gtt_mappings(i915);
> i915_gem_restore_fences(i915);
> @@ -4457,7 +4457,7 @@ void i915_gem_resume(struct drm_i915_private *i915)
> goto err_wedged;
>
> out_unlock:
> - intel_uncore_forcewake_put(i915, FORCEWAKE_ALL);
> + intel_uncore_forcewake_put(&i915->uncore, FORCEWAKE_ALL);
> mutex_unlock(&i915->drm.struct_mutex);
> return;
>
> @@ -4546,7 +4546,7 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
> dev_priv->gt.last_init_time = ktime_get();
>
> /* Double layer security blanket, see i915_gem_init() */
> - intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
>
> if (HAS_EDRAM(dev_priv) && INTEL_GEN(dev_priv) < 9)
> I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
> @@ -4601,14 +4601,14 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
> if (ret)
> goto cleanup_uc;
>
> - intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
>
> return 0;
>
> cleanup_uc:
> intel_uc_fini_hw(dev_priv);
> out:
> - intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
>
> return ret;
> }
> @@ -4812,7 +4812,7 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
> * just magically go away.
> */
> mutex_lock(&dev_priv->drm.struct_mutex);
> - intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
>
> ret = i915_gem_init_ggtt(dev_priv);
> if (ret) {
> @@ -4874,7 +4874,7 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
> goto err_init_hw;
> }
>
> - intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
> mutex_unlock(&dev_priv->drm.struct_mutex);
>
> return 0;
> @@ -4909,7 +4909,7 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
> i915_gem_fini_scratch(dev_priv);
> err_ggtt:
> err_unlock:
> - intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
> mutex_unlock(&dev_priv->drm.struct_mutex);
>
> err_uc_misc:
> diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
> index 9b0292a38865..e0fcb982a14f 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -1364,7 +1364,7 @@ static void i915_oa_stream_destroy(struct i915_perf_stream *stream)
>
> free_oa_buffer(dev_priv);
>
> - intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
> intel_runtime_pm_put(dev_priv, stream->wakeref);
>
> if (stream->ctx)
> @@ -2093,7 +2093,7 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream,
> * references will effectively disable RC6.
> */
> stream->wakeref = intel_runtime_pm_get(dev_priv);
> - intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
>
> ret = alloc_oa_buffer(dev_priv);
> if (ret)
> @@ -2127,7 +2127,7 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream,
> err_oa_buf_alloc:
> put_oa_config(dev_priv, stream->oa_config);
>
> - intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
> intel_runtime_pm_put(dev_priv, stream->wakeref);
>
> err_config:
> diff --git a/drivers/gpu/drm/i915/i915_reset.c b/drivers/gpu/drm/i915/i915_reset.c
> index 3c08e08837d0..17f569514f88 100644
> --- a/drivers/gpu/drm/i915/i915_reset.c
> +++ b/drivers/gpu/drm/i915/i915_reset.c
> @@ -569,7 +569,7 @@ int intel_gpu_reset(struct drm_i915_private *i915, unsigned int engine_mask)
> * If the power well sleeps during the reset, the reset
> * request may be dropped and never completes (causing -EIO).
> */
> - intel_uncore_forcewake_get(i915, FORCEWAKE_ALL);
> + intel_uncore_forcewake_get(&i915->uncore, FORCEWAKE_ALL);
> for (retry = 0; ret == -ETIMEDOUT && retry < retries; retry++) {
> /*
> * We stop engines, otherwise we might get failed reset and a
> @@ -593,7 +593,7 @@ int intel_gpu_reset(struct drm_i915_private *i915, unsigned int engine_mask)
> ret = reset(i915, engine_mask, retry);
> preempt_enable();
> }
> - intel_uncore_forcewake_put(i915, FORCEWAKE_ALL);
> + intel_uncore_forcewake_put(&i915->uncore, FORCEWAKE_ALL);
>
> return ret;
> }
> @@ -622,9 +622,9 @@ int intel_reset_guc(struct drm_i915_private *i915)
>
> GEM_BUG_ON(!HAS_GUC(i915));
>
> - intel_uncore_forcewake_get(i915, FORCEWAKE_ALL);
> + intel_uncore_forcewake_get(&i915->uncore, FORCEWAKE_ALL);
> ret = gen6_hw_domain_reset(i915, guc_domain);
> - intel_uncore_forcewake_put(i915, FORCEWAKE_ALL);
> + intel_uncore_forcewake_put(&i915->uncore, FORCEWAKE_ALL);
>
> return ret;
> }
> @@ -642,7 +642,7 @@ static void reset_prepare_engine(struct intel_engine_cs *engine)
> * written to the powercontext is undefined and so we may lose
> * GPU state upon resume, i.e. fail to restart after a reset.
> */
> - intel_uncore_forcewake_get(engine->i915, FORCEWAKE_ALL);
> + intel_uncore_forcewake_get(&engine->i915->uncore, FORCEWAKE_ALL);
> engine->reset.prepare(engine);
> }
>
> @@ -709,7 +709,7 @@ static int gt_reset(struct drm_i915_private *i915, unsigned int stalled_mask)
> static void reset_finish_engine(struct intel_engine_cs *engine)
> {
> engine->reset.finish(engine);
> - intel_uncore_forcewake_put(engine->i915, FORCEWAKE_ALL);
> + intel_uncore_forcewake_put(&engine->i915->uncore, FORCEWAKE_ALL);
> }
>
> struct i915_gpu_restart {
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 2b25098d47a9..4909e0ccc709 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -9498,7 +9498,7 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
> * Make sure we're not on PC8 state before disabling PC8, otherwise
> * we'll hang the machine. To prevent PC8 state, just enable force_wake.
> */
> - intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
>
> if (val & LCPLL_POWER_DOWN_ALLOW) {
> val &= ~LCPLL_POWER_DOWN_ALLOW;
> @@ -9530,7 +9530,7 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
> DRM_ERROR("Switching back to LCPLL failed\n");
> }
>
> - intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
>
> intel_update_cdclk(dev_priv);
> intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index 652c1b3ba190..588c640b5a57 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -919,7 +919,7 @@ read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
> FW_REG_READ | FW_REG_WRITE);
>
> spin_lock_irq(&dev_priv->uncore.lock);
> - intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
> + intel_uncore_forcewake_get__locked(&dev_priv->uncore, fw_domains);
>
> mcr = I915_READ_FW(GEN8_MCR_SELECTOR);
>
> @@ -937,7 +937,7 @@ read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
>
> I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
>
> - intel_uncore_forcewake_put__locked(dev_priv, fw_domains);
> + intel_uncore_forcewake_put__locked(&dev_priv->uncore, fw_domains);
> spin_unlock_irq(&dev_priv->uncore.lock);
>
> return ret;
> diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
> index 8ecb47087457..a59448a56f55 100644
> --- a/drivers/gpu/drm/i915/intel_guc.c
> +++ b/drivers/gpu/drm/i915/intel_guc.c
> @@ -369,14 +369,14 @@ void intel_guc_init_params(struct intel_guc *guc)
> * they are power context saved so it's ok to release forcewake
> * when we are done here and take it again at xfer time.
> */
> - intel_uncore_forcewake_get(dev_priv, FORCEWAKE_BLITTER);
> + intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_BLITTER);
>
> I915_WRITE(SOFT_SCRATCH(0), 0);
>
> for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
> I915_WRITE(SOFT_SCRATCH(1 + i), params[i]);
>
> - intel_uncore_forcewake_put(dev_priv, FORCEWAKE_BLITTER);
> + intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_BLITTER);
> }
>
> int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len,
> @@ -414,7 +414,7 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len,
> *action != INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER);
>
> mutex_lock(&guc->send_mutex);
> - intel_uncore_forcewake_get(dev_priv, guc->send_regs.fw_domains);
> + intel_uncore_forcewake_get(&dev_priv->uncore, guc->send_regs.fw_domains);
>
> for (i = 0; i < len; i++)
> I915_WRITE(guc_send_reg(guc, i), action[i]);
> @@ -454,7 +454,7 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len,
> ret = INTEL_GUC_MSG_TO_DATA(status);
>
> out:
> - intel_uncore_forcewake_put(dev_priv, guc->send_regs.fw_domains);
> + intel_uncore_forcewake_put(&dev_priv->uncore, guc->send_regs.fw_domains);
> mutex_unlock(&guc->send_mutex);
>
> return ret;
> diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c b/drivers/gpu/drm/i915/intel_guc_fw.c
> index 13ff7003c6be..792a551450c7 100644
> --- a/drivers/gpu/drm/i915/intel_guc_fw.c
> +++ b/drivers/gpu/drm/i915/intel_guc_fw.c
> @@ -241,7 +241,7 @@ static int guc_fw_xfer(struct intel_uc_fw *guc_fw, struct i915_vma *vma)
>
> GEM_BUG_ON(guc_fw->type != INTEL_UC_FW_TYPE_GUC);
>
> - intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
>
> guc_prepare_xfer(guc);
>
> @@ -254,7 +254,7 @@ static int guc_fw_xfer(struct intel_uc_fw *guc_fw, struct i915_vma *vma)
>
> ret = guc_xfer_ucode(guc, vma);
>
> - intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
>
> return ret;
> }
> diff --git a/drivers/gpu/drm/i915/intel_huc_fw.c b/drivers/gpu/drm/i915/intel_huc_fw.c
> index 7d7bfc7f7ca7..92799b8502f5 100644
> --- a/drivers/gpu/drm/i915/intel_huc_fw.c
> +++ b/drivers/gpu/drm/i915/intel_huc_fw.c
> @@ -112,7 +112,7 @@ static int huc_fw_xfer(struct intel_uc_fw *huc_fw, struct i915_vma *vma)
>
> GEM_BUG_ON(huc_fw->type != INTEL_UC_FW_TYPE_HUC);
>
> - intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
>
> /* Set the source address for the uCode */
> offset = intel_guc_ggtt_offset(&dev_priv->guc, vma) +
> @@ -140,7 +140,7 @@ static int huc_fw_xfer(struct intel_uc_fw *huc_fw, struct i915_vma *vma)
> /* Disable the bits once DMA is over */
> I915_WRITE(DMA_CTRL, _MASKED_BIT_DISABLE(HUC_UKERNEL));
>
> - intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
>
> return ret;
> }
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index d73b13ca57a0..007529dd161c 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -6737,9 +6737,9 @@ static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
> * punit into committing the voltage change) as that takes a lot less
> * power than the render powerwell.
> */
> - intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
> + intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_MEDIA);
> err = valleyview_set_rps(dev_priv, val);
> - intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
> + intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_MEDIA);
>
> if (err)
> DRM_ERROR("Failed to set RPS for idle\n");
> @@ -6889,11 +6889,11 @@ static void valleyview_disable_rc6(struct drm_i915_private *dev_priv)
> {
> /* We're doing forcewake before Disabling RC6,
> * This what the BIOS expects when going into suspend */
> - intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
>
> I915_WRITE(GEN6_RC_CONTROL, 0);
>
> - intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
> }
>
> static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
> @@ -7052,7 +7052,7 @@ static void reset_rps(struct drm_i915_private *dev_priv,
> /* See the Gen9_GT_PM_Programming_Guide doc for the below */
> static void gen9_enable_rps(struct drm_i915_private *dev_priv)
> {
> - intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
>
> /* Program defaults and thresholds for RPS */
> if (IS_GEN(dev_priv, 9))
> @@ -7070,7 +7070,7 @@ static void gen9_enable_rps(struct drm_i915_private *dev_priv)
> * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
> reset_rps(dev_priv, gen6_set_rps);
>
> - intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
> }
>
> static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
> @@ -7084,7 +7084,7 @@ static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
>
> /* 1b: Get forcewake during program sequence. Although the driver
> * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
> - intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
>
> /* 2a: Disable RC states. */
> I915_WRITE(GEN6_RC_CONTROL, 0);
> @@ -7161,7 +7161,7 @@ static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
> I915_WRITE(GEN9_PG_ENABLE,
> GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE);
>
> - intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
> }
>
> static void gen8_enable_rc6(struct drm_i915_private *dev_priv)
> @@ -7174,7 +7174,7 @@ static void gen8_enable_rc6(struct drm_i915_private *dev_priv)
>
> /* 1b: Get forcewake during program sequence. Although the driver
> * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
> - intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
>
> /* 2a: Disable RC states. */
> I915_WRITE(GEN6_RC_CONTROL, 0);
> @@ -7195,14 +7195,14 @@ static void gen8_enable_rc6(struct drm_i915_private *dev_priv)
> GEN7_RC_CTL_TO_MODE |
> GEN6_RC_CTL_RC6_ENABLE);
>
> - intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
> }
>
> static void gen8_enable_rps(struct drm_i915_private *dev_priv)
> {
> struct intel_rps *rps = &dev_priv->gt_pm.rps;
>
> - intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
>
> /* 1 Program defaults and thresholds for RPS*/
> I915_WRITE(GEN6_RPNSWREQ,
> @@ -7235,7 +7235,7 @@ static void gen8_enable_rps(struct drm_i915_private *dev_priv)
>
> reset_rps(dev_priv, gen6_set_rps);
>
> - intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
> }
>
> static void gen6_enable_rc6(struct drm_i915_private *dev_priv)
> @@ -7255,7 +7255,7 @@ static void gen6_enable_rc6(struct drm_i915_private *dev_priv)
> I915_WRITE(GTFIFODBG, gtfifodbg);
> }
>
> - intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
>
> /* disable the counters and set deterministic thresholds */
> I915_WRITE(GEN6_RC_CONTROL, 0);
> @@ -7303,7 +7303,7 @@ static void gen6_enable_rc6(struct drm_i915_private *dev_priv)
> DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
> }
>
> - intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
> }
>
> static void gen6_enable_rps(struct drm_i915_private *dev_priv)
> @@ -7314,7 +7314,7 @@ static void gen6_enable_rps(struct drm_i915_private *dev_priv)
> * Perhaps there might be some value in exposing these to
> * userspace...
> */
> - intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
>
> /* Power down if completely idle for over 50ms */
> I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
> @@ -7322,7 +7322,7 @@ static void gen6_enable_rps(struct drm_i915_private *dev_priv)
>
> reset_rps(dev_priv, gen6_set_rps);
>
> - intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
> }
>
> static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
> @@ -7745,7 +7745,7 @@ static void cherryview_enable_rc6(struct drm_i915_private *dev_priv)
>
> /* 1a & 1b: Get forcewake during program sequence. Although the driver
> * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
> - intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
>
> /* Disable RC states. */
> I915_WRITE(GEN6_RC_CONTROL, 0);
> @@ -7777,14 +7777,14 @@ static void cherryview_enable_rc6(struct drm_i915_private *dev_priv)
> rc6_mode = GEN7_RC_CTL_TO_MODE;
> I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
>
> - intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
> }
>
> static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
> {
> u32 val;
>
> - intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
>
> /* 1: Program defaults and thresholds for RPS*/
> I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
> @@ -7819,7 +7819,7 @@ static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
>
> reset_rps(dev_priv, valleyview_set_rps);
>
> - intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
> }
>
> static void valleyview_enable_rc6(struct drm_i915_private *dev_priv)
> @@ -7837,7 +7837,7 @@ static void valleyview_enable_rc6(struct drm_i915_private *dev_priv)
> I915_WRITE(GTFIFODBG, gtfifodbg);
> }
>
> - intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
>
> /* Disable RC states. */
> I915_WRITE(GEN6_RC_CONTROL, 0);
> @@ -7862,14 +7862,14 @@ static void valleyview_enable_rc6(struct drm_i915_private *dev_priv)
> I915_WRITE(GEN6_RC_CONTROL,
> GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL);
>
> - intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
> }
>
> static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
> {
> u32 val;
>
> - intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
>
> I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
> I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
> @@ -7903,7 +7903,7 @@ static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
>
> reset_rps(dev_priv, valleyview_set_rps);
>
> - intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
> }
>
> static unsigned long intel_pxfreq(u32 vidfreq)
> @@ -9955,7 +9955,7 @@ u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv,
> fw_domains = intel_uncore_forcewake_for_reg(dev_priv, reg, FW_REG_READ);
>
> spin_lock_irqsave(&dev_priv->uncore.lock, flags);
> - intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
> + intel_uncore_forcewake_get__locked(&dev_priv->uncore, fw_domains);
>
> /* On VLV and CHV, residency time is in CZ units rather than 1.28us */
> if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> @@ -9996,7 +9996,7 @@ u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv,
> time_hw += dev_priv->gt_pm.rc6.cur_residency[i];
> dev_priv->gt_pm.rc6.cur_residency[i] = time_hw;
>
> - intel_uncore_forcewake_put__locked(dev_priv, fw_domains);
> + intel_uncore_forcewake_put__locked(&dev_priv->uncore, fw_domains);
> spin_unlock_irqrestore(&dev_priv->uncore.lock, flags);
>
> return mul_u64_u32_div(time_hw, mul, div);
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index f26f5cc1584c..3641175baa72 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -644,7 +644,7 @@ static int init_ring_common(struct intel_engine_cs *engine)
> struct intel_ring *ring = engine->buffer;
> int ret = 0;
>
> - intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
>
> if (!stop_ring(engine)) {
> /* G45 ring initialization often fails to reset head to zero */
> @@ -731,7 +731,7 @@ static int init_ring_common(struct intel_engine_cs *engine)
> /* Papering over lost _interrupts_ immediately following the restart */
> intel_engine_queue_breadcrumbs(engine);
> out:
> - intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
>
> return ret;
> }
> @@ -2079,7 +2079,7 @@ static void gen6_bsd_submit_request(struct i915_request *request)
> {
> struct drm_i915_private *dev_priv = request->i915;
>
> - intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
>
> /* Every tail move must follow the sequence below */
>
> @@ -2109,7 +2109,7 @@ static void gen6_bsd_submit_request(struct i915_request *request)
> I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL,
> _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
>
> - intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
> }
>
> static int mi_flush_dw(struct i915_request *rq, u32 flags)
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index a2d9490739a0..75279c627388 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -608,7 +608,7 @@ static void __intel_uncore_forcewake_get(struct intel_uncore *uncore,
>
> /**
> * intel_uncore_forcewake_get - grab forcewake domain references
> - * @dev_priv: i915 device instance
> + * @uncore: the intel_uncore structure
> * @fw_domains: forcewake domains to get reference on
> *
> * This function can be used get GT's forcewake domain references.
> @@ -619,10 +619,9 @@ static void __intel_uncore_forcewake_get(struct intel_uncore *uncore,
> * call to intel_unforce_forcewake_put(). Usually caller wants all the domains
> * to be kept awake so the @fw_domains would be then FORCEWAKE_ALL.
> */
> -void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
> +void intel_uncore_forcewake_get(struct intel_uncore *uncore,
> enum forcewake_domains fw_domains)
> {
> - struct intel_uncore *uncore = &dev_priv->uncore;
> unsigned long irqflags;
>
> if (!uncore->funcs.force_wake_get)
> @@ -637,19 +636,17 @@ void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
>
> /**
> * intel_uncore_forcewake_user_get - claim forcewake on behalf of userspace
> - * @dev_priv: i915 device instance
> + * @uncore: the intel_uncore structure
> *
> * This function is a wrapper around intel_uncore_forcewake_get() to acquire
> * the GT powerwell and in the process disable our debugging for the
> * duration of userspace's bypass.
> */
> -void intel_uncore_forcewake_user_get(struct drm_i915_private *dev_priv)
> +void intel_uncore_forcewake_user_get(struct intel_uncore *uncore)
> {
> - struct intel_uncore *uncore = &dev_priv->uncore;
> -
> spin_lock_irq(&uncore->lock);
> if (!uncore->user_forcewake.count++) {
> - intel_uncore_forcewake_get__locked(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_get__locked(uncore, FORCEWAKE_ALL);
>
> /* Save and disable mmio debugging for the user bypass */
> uncore->user_forcewake.saved_mmio_check =
> @@ -665,19 +662,19 @@ void intel_uncore_forcewake_user_get(struct drm_i915_private *dev_priv)
>
> /**
> * intel_uncore_forcewake_user_put - release forcewake on behalf of userspace
> - * @dev_priv: i915 device instance
> + * @uncore: the intel_uncore structure
> *
> * This function complements intel_uncore_forcewake_user_get() and releases
> * the GT powerwell taken on behalf of the userspace bypass.
> */
> -void intel_uncore_forcewake_user_put(struct drm_i915_private *dev_priv)
> +void intel_uncore_forcewake_user_put(struct intel_uncore *uncore)
> {
> - struct intel_uncore *uncore = &dev_priv->uncore;
> + struct drm_i915_private *i915 = uncore_to_i915(uncore);
>
> spin_lock_irq(&uncore->lock);
> if (!--uncore->user_forcewake.count) {
> - if (intel_uncore_unclaimed_mmio(dev_priv))
> - dev_info(dev_priv->drm.dev,
> + if (intel_uncore_unclaimed_mmio(i915))
> + dev_info(i915->drm.dev,
> "Invalid mmio detected during user access\n");
>
> uncore->unclaimed_mmio_check =
> @@ -685,24 +682,22 @@ void intel_uncore_forcewake_user_put(struct drm_i915_private *dev_priv)
> i915_modparams.mmio_debug =
> uncore->user_forcewake.saved_mmio_debug;
>
> - intel_uncore_forcewake_put__locked(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_put__locked(uncore, FORCEWAKE_ALL);
> }
> spin_unlock_irq(&uncore->lock);
> }
>
> /**
> * intel_uncore_forcewake_get__locked - grab forcewake domain references
> - * @dev_priv: i915 device instance
> + * @uncore: the intel_uncore structure
> * @fw_domains: forcewake domains to get reference on
> *
> * See intel_uncore_forcewake_get(). This variant places the onus
> * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
> */
> -void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
> +void intel_uncore_forcewake_get__locked(struct intel_uncore *uncore,
> enum forcewake_domains fw_domains)
> {
> - struct intel_uncore *uncore = &dev_priv->uncore;
> -
> lockdep_assert_held(&uncore->lock);
>
> if (!uncore->funcs.force_wake_get)
> @@ -734,16 +729,15 @@ static void __intel_uncore_forcewake_put(struct intel_uncore *uncore,
>
> /**
> * intel_uncore_forcewake_put - release a forcewake domain reference
> - * @dev_priv: i915 device instance
> + * @uncore: the intel_uncore structure
> * @fw_domains: forcewake domains to put references
> *
> * This function drops the device-level forcewakes for specified
> * domains obtained by intel_uncore_forcewake_get().
> */
> -void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
> +void intel_uncore_forcewake_put(struct intel_uncore *uncore,
> enum forcewake_domains fw_domains)
> {
> - struct intel_uncore *uncore = &dev_priv->uncore;
> unsigned long irqflags;
>
> if (!uncore->funcs.force_wake_put)
> @@ -756,17 +750,15 @@ void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
>
> /**
> * intel_uncore_forcewake_put__locked - grab forcewake domain references
> - * @dev_priv: i915 device instance
> + * @uncore: the intel_uncore structure
> * @fw_domains: forcewake domains to get reference on
> *
> * See intel_uncore_forcewake_put(). This variant places the onus
> * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
> */
> -void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
> +void intel_uncore_forcewake_put__locked(struct intel_uncore *uncore,
> enum forcewake_domains fw_domains)
> {
> - struct intel_uncore *uncore = &dev_priv->uncore;
> -
> lockdep_assert_held(&uncore->lock);
>
> if (!uncore->funcs.force_wake_put)
> @@ -1543,11 +1535,11 @@ static int i915_pmic_bus_access_notifier(struct notifier_block *nb,
> * the access.
> */
> disable_rpm_wakeref_asserts(dev_priv);
> - intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
> enable_rpm_wakeref_asserts(dev_priv);
> break;
> case MBI_PMIC_BUS_ACCESS_END:
> - intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
> break;
> }
>
> @@ -1804,13 +1796,13 @@ int __intel_wait_for_register(struct drm_i915_private *dev_priv,
> might_sleep_if(slow_timeout_ms);
>
> spin_lock_irq(&dev_priv->uncore.lock);
> - intel_uncore_forcewake_get__locked(dev_priv, fw);
> + intel_uncore_forcewake_get__locked(&dev_priv->uncore, fw);
>
> ret = __intel_wait_for_register_fw(dev_priv,
> reg, mask, value,
> fast_timeout_us, 0, ®_value);
>
> - intel_uncore_forcewake_put__locked(dev_priv, fw);
> + intel_uncore_forcewake_put__locked(&dev_priv->uncore, fw);
> spin_unlock_irq(&dev_priv->uncore.lock);
>
> if (ret && slow_timeout_ms)
> diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
> index 86e397be9ae0..2293df59d8e9 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.h
> +++ b/drivers/gpu/drm/i915/intel_uncore.h
> @@ -167,20 +167,20 @@ intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
> #define FW_REG_READ (1)
> #define FW_REG_WRITE (2)
>
> -void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
> +void intel_uncore_forcewake_get(struct intel_uncore *uncore,
> enum forcewake_domains domains);
> -void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
> +void intel_uncore_forcewake_put(struct intel_uncore *uncore,
> enum forcewake_domains domains);
> /* Like above but the caller must manage the uncore.lock itself.
> * Must be used with I915_READ_FW and friends.
> */
> -void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
> +void intel_uncore_forcewake_get__locked(struct intel_uncore *uncore,
> enum forcewake_domains domains);
> -void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
> +void intel_uncore_forcewake_put__locked(struct intel_uncore *uncore,
> enum forcewake_domains domains);
>
> -void intel_uncore_forcewake_user_get(struct drm_i915_private *dev_priv);
> -void intel_uncore_forcewake_user_put(struct drm_i915_private *dev_priv);
> +void intel_uncore_forcewake_user_get(struct intel_uncore *uncore);
> +void intel_uncore_forcewake_user_put(struct intel_uncore *uncore);
>
> int __intel_wait_for_register(struct drm_i915_private *dev_priv,
> i915_reg_t reg,
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index 283e9a4ef3ca..e758bbf50617 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -927,7 +927,7 @@ wa_list_apply(struct drm_i915_private *dev_priv, const struct i915_wa_list *wal)
> fw = wal_get_fw_for_rmw(dev_priv, wal);
>
> spin_lock_irqsave(&dev_priv->uncore.lock, flags);
> - intel_uncore_forcewake_get__locked(dev_priv, fw);
> + intel_uncore_forcewake_get__locked(&dev_priv->uncore, fw);
>
> for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
> u32 val = I915_READ_FW(wa->reg);
> @@ -938,7 +938,7 @@ wa_list_apply(struct drm_i915_private *dev_priv, const struct i915_wa_list *wal)
> I915_WRITE_FW(wa->reg, val);
> }
>
> - intel_uncore_forcewake_put__locked(dev_priv, fw);
> + intel_uncore_forcewake_put__locked(&dev_priv->uncore, fw);
> spin_unlock_irqrestore(&dev_priv->uncore.lock, flags);
> }
>
> diff --git a/drivers/gpu/drm/i915/selftests/intel_uncore.c b/drivers/gpu/drm/i915/selftests/intel_uncore.c
> index 1c15f8d146aa..69aa260b479d 100644
> --- a/drivers/gpu/drm/i915/selftests/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/selftests/intel_uncore.c
> @@ -142,7 +142,7 @@ static int intel_uncore_check_forcewake_domains(struct drm_i915_private *dev_pri
> if (!valid)
> return -ENOMEM;
>
> - intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
>
> check_for_unclaimed_mmio(dev_priv);
> for (offset = 0; offset < FW_RANGE; offset += 4) {
> @@ -153,7 +153,7 @@ static int intel_uncore_check_forcewake_domains(struct drm_i915_private *dev_pri
> set_bit(offset, valid);
> }
>
> - intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> + intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
>
> err = 0;
> for_each_set_bit(offset, valid, FW_RANGE) {
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