On Wed, Mar 13, 2019 at 03:11:55PM +0000, Shankar, Uma wrote: > > > >-----Original Message----- > >From: Ville Syrjala [mailto:ville.syrjala@xxxxxxxxxxxxxxx] > >Sent: Tuesday, February 19, 2019 1:02 AM > >To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx > >Cc: Shankar, Uma <uma.shankar@xxxxxxxxx>; Roper, Matthew D > ><matthew.d.roper@xxxxxxxxx> > >Subject: [PATCH 2/7] drm/i915: Preocmpute/readout/check CHV CGM mode > > Typo in precompute (Hopefully) all typos fixed, and series pushed to dinq. Thanks for the review. > > > > >From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > > >Let's precompte the CGM mode for CHV. And naturally we also read it out and check > > Same here. > > Rest looks good to me. With the above minor nits fixed. > Reviewed-by: Uma Shankar <uma.shankar@xxxxxxxxx> > > >it. > > > >Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > >--- > > drivers/gpu/drm/i915/intel_color.c | 28 +++++++++++++++++++++------- > > drivers/gpu/drm/i915/intel_display.c | 8 +++++++- > > drivers/gpu/drm/i915/intel_drv.h | 9 +++++++-- > > 3 files changed, 35 insertions(+), 10 deletions(-) > > > >diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c > >index d813b9d0f5c0..93428d86510a 100644 > >--- a/drivers/gpu/drm/i915/intel_color.c > >+++ b/drivers/gpu/drm/i915/intel_color.c > >@@ -294,7 +294,6 @@ static void cherryview_load_csc_matrix(const struct > >intel_crtc_state *crtc_state > > struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); > > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > > enum pipe pipe = crtc->pipe; > >- u32 mode; > > > > if (crtc_state->base.ctm) { > > const struct drm_color_ctm *ctm = crtc_state->base.ctm->data; @@ > >-328,12 +327,7 @@ static void cherryview_load_csc_matrix(const struct > >intel_crtc_state *crtc_state > > I915_WRITE(CGM_PIPE_CSC_COEFF8(pipe), coeffs[8]); > > } > > > >- mode = (crtc_state->base.ctm ? CGM_PIPE_MODE_CSC : 0); > >- if (!crtc_state_is_legacy_gamma(crtc_state)) { > >- mode |= (crtc_state->base.degamma_lut ? > >CGM_PIPE_MODE_DEGAMMA : 0) | > >- (crtc_state->base.gamma_lut ? CGM_PIPE_MODE_GAMMA : > >0); > >- } > >- I915_WRITE(CGM_PIPE_MODE(pipe), mode); > >+ I915_WRITE(CGM_PIPE_MODE(pipe), crtc_state->cgm_mode); > > } > > > > /* Loads the legacy palette/gamma unit for the CRTC. */ @@ -753,6 +747,23 @@ > >static int check_lut_size(const struct drm_property_blob *lut, int expected) > > return 0; > > } > > > >+static u32 chv_cgm_mode(const struct intel_crtc_state *crtc_state) { > >+ u32 cgm_mode = 0; > >+ > >+ if (crtc_state_is_legacy_gamma(crtc_state)) > >+ return 0; > >+ > >+ if (crtc_state->base.degamma_lut) > >+ cgm_mode |= CGM_PIPE_MODE_DEGAMMA; > >+ if (crtc_state->base.ctm) > >+ cgm_mode |= CGM_PIPE_MODE_CSC; > >+ if (crtc_state->base.gamma_lut) > >+ cgm_mode |= CGM_PIPE_MODE_GAMMA; > >+ > >+ return cgm_mode; > >+} > >+ > > int intel_color_check(struct intel_crtc_state *crtc_state) { > > struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); > >@@ -790,6 +801,9 @@ int intel_color_check(struct intel_crtc_state *crtc_state) > > > > crtc_state->csc_mode = 0; > > > >+ if (IS_CHERRYVIEW(dev_priv)) > >+ crtc_state->cgm_mode = chv_cgm_mode(crtc_state); > >+ > > /* Always allow legacy gamma LUT with no further checking. */ > > if (!crtc_state->gamma_enable || > > crtc_state_is_legacy_gamma(crtc_state)) { diff --git > >a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > >index 2e4d33634e0c..d2f3174e10d6 100644 > >--- a/drivers/gpu/drm/i915/intel_display.c > >+++ b/drivers/gpu/drm/i915/intel_display.c > >@@ -8187,6 +8187,9 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc, > > pipe_config->gamma_mode = (tmp & > >PIPECONF_GAMMA_MODE_MASK_I9XX) >> > > PIPECONF_GAMMA_MODE_SHIFT; > > > >+ if (IS_CHERRYVIEW(dev_priv)) > >+ pipe_config->cgm_mode = I915_READ(CGM_PIPE_MODE(crtc- > >>pipe)); > >+ > > i9xx_get_pipe_color_config(pipe_config); > > > > if (INTEL_GEN(dev_priv) < 4) > >@@ -12150,7 +12153,10 @@ intel_pipe_config_compare(struct drm_i915_private > >*dev_priv, > > PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate); > > > > PIPE_CONF_CHECK_X(gamma_mode); > >- PIPE_CONF_CHECK_X(csc_mode); > >+ if (IS_CHERRYVIEW(dev_priv)) > >+ PIPE_CONF_CHECK_X(cgm_mode); > >+ else > >+ PIPE_CONF_CHECK_X(csc_mode); > > PIPE_CONF_CHECK_BOOL(gamma_enable); > > PIPE_CONF_CHECK_BOOL(csc_enable); > > } > >diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h > >index eec4ed93c335..bbe9cf7e20d6 100644 > >--- a/drivers/gpu/drm/i915/intel_drv.h > >+++ b/drivers/gpu/drm/i915/intel_drv.h > >@@ -942,8 +942,13 @@ struct intel_crtc_state { > > /* Gamma mode programmed on the pipe */ > > u32 gamma_mode; > > > >- /* CSC mode programmed on the pipe */ > >- u32 csc_mode; > >+ union { > >+ /* CSC mode programmed on the pipe */ > >+ u32 csc_mode; > >+ > >+ /* CHV CGM mode */ > >+ u32 cgm_mode; > >+ }; > > > > /* bitmask of visible planes (enum plane_id) */ > > u8 active_planes; > >-- > >2.19.2 > -- Ville Syrjälä Intel _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
