Quoting Tvrtko Ursulin (2019-03-14 14:44:19) > +struct drm_i915_engine_info { > + /** Engine class as in enum drm_i915_gem_engine_class. */ > + __u16 engine_class; > + > + /** Engine instance number. */ > + __u16 engine_instance; > + > + /** Reserved field. */ > + __u32 rsvd0; > + > + /** Engine flags. */ > + __u64 flags; > + > + /** Capabilities of this engine. */ > + __u64 capabilities; > +#define I915_VIDEO_CLASS_CAPABILITY_HEVC (1 << 0) > +#define I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC (1 << 1) > + > + /** Reserved fields. */ > + __u64 rsvd1[4]; Total of 7 __u64. Go on, just add one more. -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx