To exercise the new I915_CONTEXT_PARAM_ENGINES and interactions with
gem_execbuf().
Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
Cc: Tvrtko Ursulin <tvrtko.ursulin@xxxxxxxxxxxxxxx>
Cc: Andi Shyti <andi@xxxxxxxxxxx>
---
tests/Makefile.sources | 1 +
tests/i915/gem_ctx_engines.c | 368 +++++++++++++++++++++++++++++++++++
tests/meson.build | 1 +
3 files changed, 370 insertions(+)
create mode 100644 tests/i915/gem_ctx_engines.c
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index 9e0dab02e..41e756f15 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -21,6 +21,7 @@ TESTS_progs = \
drm_import_export \
drm_mm \
drm_read \
+ i915/gem_ctx_engines \
i915/gem_ctx_shared \
kms_3d \
kms_addfb_basic \
diff --git a/tests/i915/gem_ctx_engines.c b/tests/i915/gem_ctx_engines.c
new file mode 100644
index 000000000..acfdafa9c
--- /dev/null
+++ b/tests/i915/gem_ctx_engines.c
@@ -0,0 +1,368 @@
+/*
+ * Copyright © 2018 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include "igt.h"
+
+#include <unistd.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <string.h>
+#include <fcntl.h>
+#include <inttypes.h>
+#include <errno.h>
+#include <sys/stat.h>
+#include <sys/ioctl.h>
+#include <sys/time.h>
+
+#include <drm.h>
+
+#include "i915/gem_context.h"
+
+#define engine_class(e, n) ((e)->class_instance[(n)].engine_class)
+#define engine_instance(e, n) ((e)->class_instance[(n)].engine_instance)
+
+static bool has_context_engines(int i915)
+{
+ struct drm_i915_gem_context_param param = {
+ .ctx_id = 0,
+ .param = I915_CONTEXT_PARAM_ENGINES,
+ };
+ return __gem_context_set_param(i915, ¶m) == 0;
+}
+
+static void invalid_engines(int i915)
+{
+ struct i915_context_param_engines stack = {}, *engines;
+ struct drm_i915_gem_context_param param = {
+ .ctx_id = gem_context_create(i915),
+ .param = I915_CONTEXT_PARAM_ENGINES,
+ .value = to_user_pointer(&stack),
+ };
+ uint32_t handle;
+ void *ptr;
+
+ param.size = 0;
+ igt_assert_eq(__gem_context_set_param(i915, ¶m), 0);
+
+ param.size = 1;
+ igt_assert_eq(__gem_context_set_param(i915, ¶m), -EINVAL);
+
+ param.size = sizeof(stack) - 1;
+ igt_assert_eq(__gem_context_set_param(i915, ¶m), -EINVAL);
+
+ param.size = sizeof(stack) + 1;
+ igt_assert_eq(__gem_context_set_param(i915, ¶m), -EINVAL);
+
+ param.size = 0;
+ igt_assert_eq(__gem_context_set_param(i915, ¶m), 0);
+
+ /* Create a single page surrounded by inaccessible nothingness */
+ ptr = mmap(NULL, 3 * 4096, PROT_WRITE, MAP_ANON | MAP_PRIVATE, -1, 0);
+ igt_assert(ptr != MAP_FAILED);
+
+ munmap(ptr, 4096);
+ engines = ptr + 4096;
+ munmap(ptr + 2 *4096, 4096);
+
+ param.size = sizeof(*engines) + sizeof(*engines->class_instance);
+ param.value = to_user_pointer(engines);
+
+ engines->class_instance[0].engine_class = -1;
+ igt_assert_eq(__gem_context_set_param(i915, ¶m), -ENOENT);
+
+ mprotect(engines, 4096, PROT_READ);
+ igt_assert_eq(__gem_context_set_param(i915, ¶m), -ENOENT);
+
+ mprotect(engines, 4096, PROT_WRITE);
+ engines->class_instance[0].engine_class = 0;
+ if (__gem_context_set_param(i915, ¶m)) /* XXX needs RCS */
+ goto out;
+
+ engines->extensions = to_user_pointer(ptr);
+ igt_assert_eq(__gem_context_set_param(i915, ¶m), -EFAULT);
+
+ engines->extensions = 0;
+ igt_assert_eq(__gem_context_set_param(i915, ¶m), 0);
+
+ param.value = to_user_pointer(engines - 1);
+ igt_assert_eq(__gem_context_set_param(i915, ¶m), -EFAULT);
+
+ param.value = to_user_pointer(engines) - 1;
+ igt_assert_eq(__gem_context_set_param(i915, ¶m), -EFAULT);
+
+ param.value = to_user_pointer(engines) - param.size + 1;
+ igt_assert_eq(__gem_context_set_param(i915, ¶m), -EFAULT);
+
+ param.value = to_user_pointer(engines) + 4096;
+ igt_assert_eq(__gem_context_set_param(i915, ¶m), -EFAULT);
+
+ param.value = to_user_pointer(engines) - param.size + 4096;
+ igt_assert_eq(__gem_context_set_param(i915, ¶m), 0);
+
+ param.value = to_user_pointer(engines) - param.size + 4096 + 1;
+ igt_assert_eq(__gem_context_set_param(i915, ¶m), -EFAULT);
+
+ param.value = to_user_pointer(engines) + 4096;
+ igt_assert_eq(__gem_context_set_param(i915, ¶m), -EFAULT);
+
+ param.value = to_user_pointer(engines) + 4096 - 1;
+ igt_assert_eq(__gem_context_set_param(i915, ¶m), -EFAULT);
+
+ param.value = to_user_pointer(engines) - 1;
+ igt_assert_eq(__gem_context_set_param(i915, ¶m), -EFAULT);
+
+ param.value = to_user_pointer(engines - 1);
+ igt_assert_eq(__gem_context_set_param(i915, ¶m), -EFAULT);
+
+ param.value = to_user_pointer(engines - 1) + 4096;
+ igt_assert_eq(__gem_context_set_param(i915, ¶m), -EFAULT);
+
+ param.value = to_user_pointer(engines - 1) + 4096 - sizeof(*engines->class_instance) / 2;
+ igt_assert_eq(__gem_context_set_param(i915, ¶m), -EFAULT);
+
+ handle = gem_create(i915, 4096 * 3);
+ ptr = gem_mmap__gtt(i915, handle, 4096 * 3, PROT_READ);
+ gem_close(i915, handle);
+
+ munmap(ptr, 4096);
+ munmap(ptr + 8192, 4096);
+
+ param.value = to_user_pointer(ptr + 4096);
+ igt_assert_eq(__gem_context_set_param(i915, ¶m), 0);
+
+ param.value = to_user_pointer(ptr);
+ igt_assert_eq(__gem_context_set_param(i915, ¶m), -EFAULT);
+
+ param.value = to_user_pointer(ptr) + 4095;
+ igt_assert_eq(__gem_context_set_param(i915, ¶m), -EFAULT);
+
+ param.value = to_user_pointer(ptr) + 8192;
+ igt_assert_eq(__gem_context_set_param(i915, ¶m), -EFAULT);
+
+ param.value = to_user_pointer(ptr) + 12287;
+ igt_assert_eq(__gem_context_set_param(i915, ¶m), -EFAULT);
+
+ munmap(ptr + 4096, 4096);
+
+out:
+ munmap(engines, 4096);
+ gem_context_destroy(i915, param.ctx_id);
+}
+
+static void execute_one(int i915)
+{
+ I915_DEFINE_CONTEXT_PARAM_ENGINES(engines , I915_EXEC_RING_MASK + 1);
+ struct drm_i915_gem_context_param param = {
+ .ctx_id = gem_context_create(i915),
+ .param = I915_CONTEXT_PARAM_ENGINES,
+ .value = to_user_pointer(&engines),
+ /* .size to be filled in later */
+ };
+ struct drm_i915_gem_exec_object2 obj = {
+ .handle = gem_create(i915, 4096),
+ };
+ struct drm_i915_gem_execbuffer2 execbuf = {
+ .buffers_ptr = to_user_pointer(&obj),
+ .buffer_count = 1,
+ .rsvd1 = param.ctx_id,
+ };
+ const uint32_t bbe = MI_BATCH_BUFFER_END;
+ const struct intel_execution_engine2 *e;
+
+ gem_write(i915, obj.handle, 0, &bbe, sizeof(bbe));
+
+ /* Unadulterated I915_EXEC_DEFAULT should work */
+ execbuf.flags = 0;
+ igt_assert_eq(__gem_execbuf(i915, &execbuf), 0);
+ gem_sync(i915, obj.handle);
+
+ for_each_engine_class_instance(i915, e) {
+ struct drm_i915_gem_busy busy = { .handle = obj.handle };
+
+ for (int i = -1; i <= I915_EXEC_RING_MASK; i++) {
+ igt_spin_t *spin;
+
+ memset(&engines, 0, sizeof(engines));
+ engine_class(&engines, 0) = e->class;
+ engine_instance(&engines, 0) = e->instance;
+ param.size = offsetof(typeof(engines), class_instance[1]);
+ gem_context_set_param(i915, ¶m);
+
+ spin = igt_spin_batch_new(i915,
+ .ctx = param.ctx_id,
+ .engine = 0);
+
+ igt_debug("Testing with map of %d engines\n", i + 1);
+ memset(&engines.class_instance, -1, sizeof(engines.class_instance));
+ if (i != -1) {
+ engine_class(&engines, i) = e->class;
+ engine_instance(&engines, i) = e->instance;
+ }
+ param.size = sizeof(uint64_t) + (i + 1) * sizeof(uint32_t);
+ gem_context_set_param(i915, ¶m);
+
+ for (int j = 0; j <= I915_EXEC_RING_MASK; j++) {
+ int err;
+
+ execbuf.flags = j;
+ err =__gem_execbuf(i915, &execbuf);
+ if (j == i) {
+ igt_assert_f(err == 0,
+ "Failed to report the valid engine for slot %d\n",
+ i);
+ } else {
+ igt_assert_f(err == -EINVAL,
+ "Failed to report an invalid engine for slot %d (valid at %d)\n",
+ j, i);
+ }
+ }
+
+ do_ioctl(i915, DRM_IOCTL_I915_GEM_BUSY, &busy);
+ if (i != -1) {
+ igt_assert_eq(busy.busy, 1 << (e->class + 16));
+ } else {
+ igt_assert_eq(busy.busy, 0);
+ }
+
+ igt_spin_batch_free(i915, spin);
+
+ gem_sync(i915, obj.handle);
+ do_ioctl(i915, DRM_IOCTL_I915_GEM_BUSY, &busy);
+ igt_assert_eq(busy.busy, 0);
+ }
+ }
+
+ /* Restore the defaults and check I915_EXEC_DEFAULT works again. */
+ param.size = 0;
+ gem_context_set_param(i915, ¶m);
+ execbuf.flags = 0;
+ igt_assert_eq(__gem_execbuf(i915, &execbuf), 0);
+
+ gem_close(i915, obj.handle);
+ gem_context_destroy(i915, param.ctx_id);
+}
+
+static void execute_oneforall(int i915)
+{
+ I915_DEFINE_CONTEXT_PARAM_ENGINES(engines , I915_EXEC_RING_MASK + 1);
+ struct drm_i915_gem_context_param param = {
+ .ctx_id = gem_context_create(i915),
+ .param = I915_CONTEXT_PARAM_ENGINES,
+ .value = to_user_pointer(&engines),
+ .size = sizeof(engines),
+ };
+ const struct intel_execution_engine2 *e;
+
+ for_each_engine_class_instance(i915, e) {
+ memset(&engines, 0, sizeof(engines));
+ for (int i = 0; i <= I915_EXEC_RING_MASK; i++) {
+ engine_class(&engines, i) = e->class;
+ engine_instance(&engines, i) = e->instance;
+ }
+ gem_context_set_param(i915, ¶m);
+
+ for (int i = 0; i <= I915_EXEC_RING_MASK; i++) {
+ struct drm_i915_gem_busy busy = {};
+ igt_spin_t *spin;
+
+ spin = __igt_spin_batch_new(i915,
+ .ctx = param.ctx_id,
+ .engine = i);
+
+ busy.handle = spin->handle;
+ do_ioctl(i915, DRM_IOCTL_I915_GEM_BUSY, &busy);
+ igt_assert_eq(busy.busy, 1 << (e->class + 16));
+
+ igt_spin_batch_free(i915, spin);
+ }
+ }
+
+ gem_context_destroy(i915, param.ctx_id);
+}
+
+static void execute_allforone(int i915)
+{
+ I915_DEFINE_CONTEXT_PARAM_ENGINES(engines , I915_EXEC_RING_MASK + 1);
+ struct drm_i915_gem_context_param param = {
+ .ctx_id = gem_context_create(i915),
+ .param = I915_CONTEXT_PARAM_ENGINES,
+ .value = to_user_pointer(&engines),
+ };
+ const struct intel_execution_engine2 *e;
+ int i;
+
+ i = 0;
+ memset(&engines, 0, sizeof(engines));
+ for_each_engine_class_instance(i915, e) {
+ engine_class(&engines, i) = e->class;
+ engine_instance(&engines, i) = e->instance;
+ i++;
+ }
+ param.size = sizeof(uint64_t) + i * sizeof(uint32_t);
+ gem_context_set_param(i915, ¶m);
+
+ i = 0;
+ for_each_engine_class_instance(i915, e) {
+ struct drm_i915_gem_busy busy = {};
+ igt_spin_t *spin;
+
+ spin = __igt_spin_batch_new(i915,
+ .ctx = param.ctx_id,
+ .engine = i++);
+
+ busy.handle = spin->handle;
+ do_ioctl(i915, DRM_IOCTL_I915_GEM_BUSY, &busy);
+ igt_assert_eq(busy.busy, 1 << (e->class + 16));
+
+ igt_spin_batch_free(i915, spin);
+ }
+
+ gem_context_destroy(i915, param.ctx_id);
+}
+
+igt_main
+{
+ int i915 = -1;
+
+ igt_fixture {
+ i915 = drm_open_driver_render(DRIVER_INTEL);
+ igt_require_gem(i915);
+
+ gem_require_contexts(i915);
+ igt_require(has_context_engines(i915));
+ }
+
+ igt_subtest("invalid-engines")
+ invalid_engines(i915);
+
+ igt_subtest("execute-one")
+ execute_one(i915);
+
+ igt_subtest("execute-oneforall")
+ execute_oneforall(i915);
+
+ igt_subtest("execute-allforone")
+ execute_allforone(i915);
+}
diff --git a/tests/meson.build b/tests/meson.build
index 017df8718..0539c20c8 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -109,6 +109,7 @@ i915_progs = [
'gem_cs_tlb',
'gem_ctx_bad_destroy',
'gem_ctx_create',
+ 'gem_ctx_engines',
'gem_ctx_exec',
'gem_ctx_isolation',
'gem_ctx_param',
--
2.20.1
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