On Wed, Feb 27, 2019 at 08:50:31PM +0000, Chris Wilson wrote: > Quoting Jani Nikula (2019-02-27 17:02:36) <snip> > > #define PP_REFERENCE_DIVIDER_SHIFT 8 > > -#define PANEL_POWER_CYCLE_DELAY_MASK 0x1f > > +#define PANEL_POWER_CYCLE_DELAY_MASK REG_GENMASK(4, 0) > > Ok. > > I'll get used to the hi,lo convention eventually. The nice thing is that it matches the spec. The hard part is running out of fingers for wide bitfields :P -- Ville Syrjälä Intel _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
