Quoting Tvrtko Ursulin (2019-02-26 07:34:37) > > On 25/02/2019 18:40, Chris Wilson wrote: > > Quoting Tvrtko Ursulin (2019-02-25 17:59:40) > >> > >> On 25/02/2019 16:23, Chris Wilson wrote: > >>> static inline struct i915_priolist *to_priolist(struct rb_node *rb) > >>> { > >>> return rb_entry(rb, struct i915_priolist, node); > >>> @@ -2206,6 +2212,10 @@ static u32 *gen8_emit_fini_breadcrumb(struct i915_request *request, u32 *cs) > >>> request->fence.seqno, > >>> request->timeline->hwsp_offset); > >>> > >>> + cs = gen8_emit_ggtt_write(cs, > >>> + intel_engine_next_hangcheck_seqno(request->engine), > >>> + intel_hws_hangcheck_address(request->engine)); > >>> + > >>> cs = gen8_emit_ggtt_write(cs, > >>> request->global_seqno, > >>> intel_hws_seqno_address(request->engine)); > >>> @@ -2230,6 +2240,11 @@ static u32 *gen8_emit_fini_breadcrumb_rcs(struct i915_request *request, u32 *cs) > >>> PIPE_CONTROL_FLUSH_ENABLE | > >>> PIPE_CONTROL_CS_STALL); > >>> > >>> + cs = gen8_emit_ggtt_write_rcs(cs, > >>> + intel_engine_next_hangcheck_seqno(request->engine), > >>> + intel_hws_hangcheck_address(request->engine), > >>> + PIPE_CONTROL_CS_STALL); > >> > >> Are CS_STALL needed on two writes or only last one would be enough? Or > >> even, should all flushes be moved to the last pipe control? > > > > The CS_STALL is overkill as there's no requirement for it to be before > > the global_seqno, but the convenience and ease to reason over win. [snip] > Ok have at it. > > Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@xxxxxxxxx> I was just about to resend without the CS_STALL... -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx