Verify that our list of nonpriv registers exist and are writable.
Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
---
tests/i915/gem_ctx_isolation.c | 254 ++++++++++++++++++--------
tests/intel-ci/fast-feedback.testlist | 5 +
2 files changed, 178 insertions(+), 81 deletions(-)
diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c
index 839d49ade..63b5ee61c 100644
--- a/tests/i915/gem_ctx_isolation.c
+++ b/tests/i915/gem_ctx_isolation.c
@@ -59,96 +59,97 @@ enum {
static const struct named_register {
const char *name;
- unsigned int gen_mask;
- unsigned int engine_mask;
- uint32_t offset;
+ unsigned int read_mask; /* on which gen the register exists */
+ unsigned int write_mask; /* but it may only be writable on some gen! */
+ unsigned int engine_mask; /* preferred engine / powerwell */
+ uint32_t offset; /* address of register, from bottom of mmio bar */
uint32_t count;
uint32_t ignore_bits;
bool masked;
} nonpriv_registers[] = {
- { "NOPID", NOCTX, RCS0, 0x2094 },
- { "MI_PREDICATE_RESULT_2", NOCTX, RCS0, 0x23bc },
- { "INSTPM", GEN6, RCS0, 0x20c0, 1, BIT(8) /* ro counter */, true },
- { "IA_VERTICES_COUNT", GEN4, RCS0, 0x2310, 2 },
- { "IA_PRIMITIVES_COUNT", GEN4, RCS0, 0x2318, 2 },
- { "VS_INVOCATION_COUNT", GEN4, RCS0, 0x2320, 2 },
- { "HS_INVOCATION_COUNT", GEN4, RCS0, 0x2300, 2 },
- { "DS_INVOCATION_COUNT", GEN4, RCS0, 0x2308, 2 },
- { "GS_INVOCATION_COUNT", GEN4, RCS0, 0x2328, 2 },
- { "GS_PRIMITIVES_COUNT", GEN4, RCS0, 0x2330, 2 },
- { "CL_INVOCATION_COUNT", GEN4, RCS0, 0x2338, 2 },
- { "CL_PRIMITIVES_COUNT", GEN4, RCS0, 0x2340, 2 },
- { "PS_INVOCATION_COUNT_0", GEN4, RCS0, 0x22c8, 2 },
- { "PS_DEPTH_COUNT_0", GEN4, RCS0, 0x22d8, 2 },
- { "GPUGPU_DISPATCHDIMX", GEN8, RCS0, 0x2500 },
- { "GPUGPU_DISPATCHDIMY", GEN8, RCS0, 0x2504 },
- { "GPUGPU_DISPATCHDIMZ", GEN8, RCS0, 0x2508 },
- { "MI_PREDICATE_SRC0", GEN8, RCS0, 0x2400, 2 },
- { "MI_PREDICATE_SRC1", GEN8, RCS0, 0x2408, 2 },
- { "MI_PREDICATE_DATA", GEN8, RCS0, 0x2410, 2 },
- { "MI_PRED_RESULT", GEN8, RCS0, 0x2418 },
- { "3DPRIM_END_OFFSET", GEN6, RCS0, 0x2420 },
- { "3DPRIM_START_VERTEX", GEN6, RCS0, 0x2430 },
- { "3DPRIM_VERTEX_COUNT", GEN6, RCS0, 0x2434 },
- { "3DPRIM_INSTANCE_COUNT", GEN6, RCS0, 0x2438 },
- { "3DPRIM_START_INSTANCE", GEN6, RCS0, 0x243c },
- { "3DPRIM_BASE_VERTEX", GEN6, RCS0, 0x2440 },
- { "GPGPU_THREADS_DISPATCHED", GEN8, RCS0, 0x2290, 2 },
- { "PS_INVOCATION_COUNT_1", GEN8, RCS0, 0x22f0, 2 },
- { "PS_DEPTH_COUNT_1", GEN8, RCS0, 0x22f8, 2 },
- { "BB_OFFSET", GEN8, RCS0, 0x2158, .ignore_bits = 0x4 },
- { "MI_PREDICATE_RESULT_1", GEN8, RCS0, 0x241c },
- { "CS_GPR", GEN8, RCS0, 0x2600, 32 },
- { "OA_CTX_CONTROL", GEN8, RCS0, 0x2360 },
- { "OACTXID", GEN8, RCS0, 0x2364 },
- { "PS_INVOCATION_COUNT_2", GEN8, RCS0, 0x2448, 2 },
- { "PS_DEPTH_COUNT_2", GEN8, RCS0, 0x2450, 2 },
- { "Cache_Mode_0", GEN7, RCS0, 0x7000 },
- { "Cache_Mode_1", GEN7, RCS0, 0x7004 },
- { "GT_MODE", GEN8, RCS0, 0x7008 },
- { "L3_Config", GEN7, RCS0, 0x7034 },
- { "TD_CTL", GEN8, RCS0, 0xe400 },
- { "TD_CTL2", GEN8, RCS0, 0xe404 },
- { "SO_NUM_PRIMS_WRITEN0", GEN6, RCS0, 0x5200, 2 },
- { "SO_NUM_PRIMS_WRITEN1", GEN6, RCS0, 0x5208, 2 },
- { "SO_NUM_PRIMS_WRITEN2", GEN6, RCS0, 0x5210, 2 },
- { "SO_NUM_PRIMS_WRITEN3", GEN6, RCS0, 0x5218, 2 },
- { "SO_PRIM_STORAGE_NEEDED0", GEN6, RCS0, 0x5240, 2 },
- { "SO_PRIM_STORAGE_NEEDED1", GEN6, RCS0, 0x5248, 2 },
- { "SO_PRIM_STORAGE_NEEDED2", GEN6, RCS0, 0x5250, 2 },
- { "SO_PRIM_STORAGE_NEEDED3", GEN6, RCS0, 0x5258, 2 },
- { "SO_WRITE_OFFSET0", GEN7, RCS0, 0x5280 },
- { "SO_WRITE_OFFSET1", GEN7, RCS0, 0x5284 },
- { "SO_WRITE_OFFSET2", GEN7, RCS0, 0x5288 },
- { "SO_WRITE_OFFSET3", GEN7, RCS0, 0x528c },
- { "OA_CONTROL", NOCTX, RCS0, 0x2b00 },
- { "PERF_CNT_1", NOCTX, RCS0, 0x91b8, 2 },
- { "PERF_CNT_2", NOCTX, RCS0, 0x91c0, 2 },
+ { "NOPID", NOCTX, -1, RCS0, 0x2094 },
+ { "MI_PREDICATE_RESULT_2", NOCTX, -1, RCS0, 0x23bc },
+ { "INSTPM", GEN6, 0 /* rsvd bits vary by gen */, RCS0, 0x20c0, 1, BIT(8) /* r/o counter */, true },
+ { "IA_VERTICES_COUNT", GEN4, GEN8, RCS0, 0x2310, 2 },
+ { "IA_PRIMITIVES_COUNT", GEN4, GEN8, RCS0, 0x2318, 2 },
+ { "VS_INVOCATION_COUNT", GEN4, GEN8, RCS0, 0x2320, 2 },
+ { "HS_INVOCATION_COUNT", GEN4, GEN8, RCS0, 0x2300, 2 },
+ { "DS_INVOCATION_COUNT", GEN4, GEN8, RCS0, 0x2308, 2 },
+ { "GS_INVOCATION_COUNT", GEN4, GEN8, RCS0, 0x2328, 2 },
+ { "GS_PRIMITIVES_COUNT", GEN4, GEN8, RCS0, 0x2330, 2 },
+ { "CL_INVOCATION_COUNT", GEN4, GEN8, RCS0, 0x2338, 2 },
+ { "CL_PRIMITIVES_COUNT", GEN4, GEN8, RCS0, 0x2340, 2 },
+ { "PS_INVOCATION_COUNT_0", GEN4, GEN8, RCS0, 0x22c8, 2, .ignore_bits = 0x3 },
+ { "PS_DEPTH_COUNT_0", GEN4, GEN8, RCS0, 0x22d8, 2 },
+ { "GPUGPU_DISPATCHDIMX", GEN8, -1, RCS0, 0x2500 },
+ { "GPUGPU_DISPATCHDIMY", GEN8, -1, RCS0, 0x2504 },
+ { "GPUGPU_DISPATCHDIMZ", GEN8, -1, RCS0, 0x2508 },
+ { "MI_PREDICATE_SRC0", GEN8, -1, RCS0, 0x2400, 2 },
+ { "MI_PREDICATE_SRC1", GEN8, -1, RCS0, 0x2408, 2 },
+ { "MI_PREDICATE_DATA", GEN8, -1, RCS0, 0x2410, 2 },
+ { "MI_PRED_RESULT", GEN8, -1, RCS0, 0x2418, .ignore_bits = ~1u },
+ { "3DPRIM_END_OFFSET", GEN6, GEN7, RCS0, 0x2420 },
+ { "3DPRIM_START_VERTEX", GEN6, GEN7, RCS0, 0x2430 },
+ { "3DPRIM_VERTEX_COUNT", GEN6, GEN7, RCS0, 0x2434 },
+ { "3DPRIM_INSTANCE_COUNT", GEN6, GEN7, RCS0, 0x2438 },
+ { "3DPRIM_START_INSTANCE", GEN6, GEN7, RCS0, 0x243c },
+ { "3DPRIM_BASE_VERTEX", GEN6, GEN7, RCS0, 0x2440 },
+ { "GPGPU_THREADS_DISPATCHED", GEN8, -1, RCS0, 0x2290, 2 },
+ { "PS_INVOCATION_COUNT_1", GEN8, -1, RCS0, 0x22f0, 2, .ignore_bits = 0x3 },
+ { "PS_DEPTH_COUNT_1", GEN8, -1, RCS0, 0x22f8, 2 },
+ { "BB_OFFSET", GEN8, -1, RCS0, 0x2158, .ignore_bits = 0x4 },
+ { "MI_PREDICATE_RESULT_1", GEN8, -1, RCS0, 0x241c },
+ { "CS_GPR", GEN8, -1, RCS0, 0x2600, 32 },
+ { "OA_CTX_CONTROL", GEN8, -1, RCS0, 0x2360 },
+ { "OACTXID", GEN8, -1, RCS0, 0x2364 },
+ { "PS_INVOCATION_COUNT_2", GEN8, -1, RCS0, 0x2448, 2, .ignore_bits = 0x3 },
+ { "PS_DEPTH_COUNT_2", GEN8, -1, RCS0, 0x2450, 2 },
+ { "Cache_Mode_0", GEN7, GEN8, RCS0, 0x7000, .masked = true },
+ { "Cache_Mode_1", GEN7, GEN8, RCS0, 0x7004, .masked = true },
+ { "GT_MODE", GEN8, -1, RCS0, 0x7008, .masked = true },
+ { "L3_Config", GEN8, -1, RCS0, 0x7034 },
+ { "TD_CTL", GEN8, -1, RCS0, 0xe400, .masked = true },
+ { "TD_CTL2", GEN8, -1, RCS0, 0xe404 },
+ { "SO_NUM_PRIMS_WRITTEN0", GEN6, GEN7, RCS0, 0x5200, 2 },
+ { "SO_NUM_PRIMS_WRITTEN1", GEN6, GEN7, RCS0, 0x5208, 2 },
+ { "SO_NUM_PRIMS_WRITTEN2", GEN6, GEN7, RCS0, 0x5210, 2 },
+ { "SO_NUM_PRIMS_WRITTEN3", GEN6, GEN7, RCS0, 0x5218, 2 },
+ { "SO_PRIM_STORAGE_NEEDED0", GEN6, GEN7, RCS0, 0x5240, 2 },
+ { "SO_PRIM_STORAGE_NEEDED1", GEN6, GEN7, RCS0, 0x5248, 2 },
+ { "SO_PRIM_STORAGE_NEEDED2", GEN6, GEN7, RCS0, 0x5250, 2 },
+ { "SO_PRIM_STORAGE_NEEDED3", GEN6, GEN7, RCS0, 0x5258, 2 },
+ { "SO_WRITE_OFFSET0", GEN7, -1, RCS0, 0x5280, .ignore_bits = 0x3 },
+ { "SO_WRITE_OFFSET1", GEN7, -1, RCS0, 0x5284, .ignore_bits = 0x3 },
+ { "SO_WRITE_OFFSET2", GEN7, -1, RCS0, 0x5288, .ignore_bits = 0x3 },
+ { "SO_WRITE_OFFSET3", GEN7, -1, RCS0, 0x528c, .ignore_bits = 0x3 },
+ { "OA_CONTROL", NOCTX, -1, RCS0, 0x2b00 },
+ { "PERF_CNT_1", NOCTX, -1, RCS0, 0x91b8, 2 },
+ { "PERF_CNT_2", NOCTX, -1, RCS0, 0x91c0, 2 },
/* Privileged (enabled by w/a + FORCE_TO_NONPRIV) */
- { "CTX_PREEMPT", NOCTX /* GEN_RANGE(9, 10) */, RCS0, 0x2248 },
- { "CS_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x2580 },
- { "HDC_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x7304 },
- { "L3SQREG1", GEN8, RCS0, 0xb010 },
+ { "CTX_PREEMPT", NOCTX /* GEN_RANGE(9, 10) */, -1, RCS0, 0x2248 },
+ { "CS_CHICKEN1", GEN_RANGE(9, 10), -1, RCS0, 0x2580, .masked = true },
+ { "HDC_CHICKEN1", GEN_RANGE(9, 10), -1, RCS0, 0x7304, .masked = true },
+ { "L3SQREG4", GEN9, -1, RCS0, 0xb118, .ignore_bits = 0x1ffff0 },
- { "BCS_GPR", GEN9, BCS0, 0x22600, 32 },
- { "BCS_SWCTRL", GEN8, BCS0, 0x22200 },
+ { "BCS_GPR", GEN9, -1, BCS0, 0x22600, 32 },
+ { "BCS_SWCTRL", GEN8, -1, BCS0, 0x22200, .ignore_bits = ~0x3, .masked = true },
- { "VCS0_GPR", GEN9, VCS0, 0x12600, 32 },
- { "MFC_VDBOX1", NOCTX, VCS0, 0x12800, 64 },
+ { "VCS0_GPR", GEN9, -1, VCS0, 0x12600, 32 },
+ { "MFC_VDBOX1", NOCTX, -1, VCS0, 0x12800, 64 },
- { "VCS1_GPR", GEN9, VCS1, 0x1c600, 32 },
- { "MFC_VDBOX2", NOCTX, VCS1, 0x1c800, 64 },
+ { "VCS1_GPR", GEN9, -1, VCS1, 0x1c600, 32 },
+ { "MFC_VDBOX2", NOCTX, -1, VCS1, 0x1c800, 64 },
- { "VECS_GPR", GEN9, VECS0, 0x1a600, 32 },
+ { "VECS_GPR", GEN9, -1, VECS0, 0x1a600, 32 },
{}
}, ignore_registers[] = {
- { "RCS timestamp", GEN6, ~0u, 0x2358 },
- { "VCS0 timestamp", GEN7, ~0u, 0x12358 },
- { "VCS1 timestamp", GEN7, ~0u, 0x1c358 },
- { "BCS timestamp", GEN7, ~0u, 0x22358 },
- { "VECS timestamp", GEN8, ~0u, 0x1a358 },
+ { "RCS timestamp", GEN6, -1, ~0u, 0x2358 },
+ { "VCS0 timestamp", GEN7, -1, ~0u, 0x12358 },
+ { "VCS1 timestamp", GEN7, -1, ~0u, 0x1c358 },
+ { "BCS timestamp", GEN7, -1, ~0u, 0x22358 },
+ { "VECS timestamp", GEN8, -1, ~0u, 0x1a358 },
{}
};
@@ -191,6 +192,40 @@ static bool ignore_register(uint32_t offset)
return false;
}
+static void tmpl_regs(int fd,
+ uint32_t ctx,
+ const struct intel_execution_engine2 *e,
+ uint32_t handle,
+ uint32_t value)
+{
+ const unsigned int gen_bit = 1 << intel_gen(intel_get_drm_devid(fd));
+ const unsigned int engine_bit = ENGINE(e->class, e->instance);
+ unsigned int regs_size;
+ uint32_t *regs;
+
+ regs_size = NUM_REGS * sizeof(uint32_t);
+ regs_size = PAGE_ALIGN(regs_size);
+
+ regs = gem_mmap__cpu(fd, handle, 0, regs_size, PROT_WRITE);
+ gem_set_domain(fd, handle,
+ I915_GEM_DOMAIN_CPU, I915_GEM_DOMAIN_CPU);
+
+ for (const struct named_register *r = nonpriv_registers; r->name; r++) {
+ if (!(r->engine_mask & engine_bit))
+ continue;
+ if (!(r->write_mask & r->read_mask & gen_bit))
+ continue;
+ for (unsigned count = r->count ?: 1, offset = r->offset;
+ count--; offset += 4) {
+ if (r->masked)
+ regs[offset/sizeof(*regs)] = value & 0xffff;
+ else
+ regs[offset/sizeof(*regs)] = value;
+ }
+ }
+ munmap(regs, regs_size);
+}
+
static uint32_t read_regs(int fd,
uint32_t ctx,
const struct intel_execution_engine2 *e,
@@ -228,7 +263,7 @@ static uint32_t read_regs(int fd,
for (const struct named_register *r = nonpriv_registers; r->name; r++) {
if (!(r->engine_mask & engine_bit))
continue;
- if (!(r->gen_mask & gen_bit))
+ if (!(r->read_mask & gen_bit))
continue;
for (unsigned count = r->count ?: 1, offset = r->offset;
@@ -290,7 +325,7 @@ static void write_regs(int fd,
for (const struct named_register *r = nonpriv_registers; r->name; r++) {
if (!(r->engine_mask & engine_bit))
continue;
- if (!(r->gen_mask & gen_bit))
+ if (!(r->write_mask & r->read_mask & gen_bit))
continue;
for (unsigned count = r->count ?: 1, offset = r->offset;
count--; offset += 4) {
@@ -353,7 +388,7 @@ static void restore_regs(int fd,
for (const struct named_register *r = nonpriv_registers; r->name; r++) {
if (!(r->engine_mask & engine_bit))
continue;
- if (!(r->gen_mask & gen_bit))
+ if (!(r->write_mask & r->read_mask & gen_bit))
continue;
for (unsigned count = r->count ?: 1, offset = r->offset;
@@ -406,7 +441,7 @@ static void dump_regs(int fd,
for (const struct named_register *r = nonpriv_registers; r->name; r++) {
if (!(r->engine_mask & engine_bit))
continue;
- if (!(r->gen_mask & gen_bit))
+ if (!(r->read_mask & gen_bit))
continue;
if (r->count <= 1) {
@@ -474,6 +509,60 @@ static void compare_regs(int fd, uint32_t A, uint32_t B, const char *who)
num_errors, who);
}
+static void nonpriv(int fd,
+ const struct intel_execution_engine2 *e,
+ unsigned int flags)
+{
+ static const uint32_t values[] = {
+ 0x0,
+ 0xffffffff,
+ 0xcccccccc,
+ 0x33333333,
+ 0x55555555,
+ 0xaaaaaaaa,
+ 0xdeadbeef
+ };
+ unsigned int engine =
+ gem_class_instance_to_eb_flags(fd, e->class, e->instance);
+ unsigned int num_values = ARRAY_SIZE(values);
+
+ gem_quiescent_gpu(fd);
+
+ for (int v = 0; v < num_values; v++) {
+ igt_spin_t *spin = NULL;
+ uint32_t ctx, regs[2], tmpl;
+
+ ctx = gem_context_create(fd);
+ tmpl = read_regs(fd, ctx, e, flags);
+ regs[0] = read_regs(fd, ctx, e, flags);
+
+ tmpl_regs(fd, ctx, e, tmpl, values[v]);
+
+ spin = igt_spin_batch_new(fd, .ctx = ctx, .engine = engine);
+
+ igt_debug("%s[%d]: Setting all registers to 0x%08x\n",
+ __func__, v, values[v]);
+ write_regs(fd, ctx, e, flags, values[v]);
+
+ regs[1] = read_regs(fd, ctx, e, flags);
+
+ /*
+ * Restore the original register values before the HW idles.
+ * Or else it may never restart!
+ */
+ restore_regs(fd, ctx, e, flags, regs[0]);
+
+ igt_spin_batch_free(fd, spin);
+
+ compare_regs(fd, tmpl, regs[1], "nonpriv read/writes");
+
+ for (int n = 0; n < ARRAY_SIZE(regs); n++)
+ gem_close(fd, regs[n]);
+ gem_context_destroy(fd, ctx);
+ gem_close(fd, tmpl);
+ }
+}
+
static void isolation(int fd,
const struct intel_execution_engine2 *e,
unsigned int flags)
@@ -715,6 +804,9 @@ igt_main
igt_fork_hang_detector(fd);
}
+ igt_subtest_f("%s-nonpriv", e->name)
+ nonpriv(fd, e, 0);
+
igt_subtest_f("%s-clean", e->name)
isolation(fd, e, 0);
igt_subtest_f("%s-dirty-create", e->name)
diff --git a/tests/intel-ci/fast-feedback.testlist b/tests/intel-ci/fast-feedback.testlist
index 2d22c2c1c..87eb8bbb9 100644
--- a/tests/intel-ci/fast-feedback.testlist
+++ b/tests/intel-ci/fast-feedback.testlist
@@ -12,6 +12,11 @@ igt@gem_close_race@basic-threads
igt@gem_cpu_reloc@basic
igt@gem_ctx_create@basic
igt@gem_ctx_create@basic-files
+igt@gem_ctx_isolation@rcs0-nonpriv
+igt@gem_ctx_isolation@bcs0-nonpriv
+igt@gem_ctx_isolation@vcs0-nonpriv
+igt@gem_ctx_isolation@vcs1-nonpriv
+igt@gem_ctx_isolation@vecs0-nonpriv
igt@gem_ctx_exec@basic
igt@gem_ctx_param@basic
igt@gem_ctx_param@basic-default
--
2.20.1
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