Needs a quick verification pass... Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> --- tests/i915/gem_ctx_isolation.c | 129 ++++++++++++++++++++++---- tests/intel-ci/fast-feedback.testlist | 5 + 2 files changed, 117 insertions(+), 17 deletions(-) diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c index 839d49ade..0c90d6590 100644 --- a/tests/i915/gem_ctx_isolation.c +++ b/tests/i915/gem_ctx_isolation.c @@ -68,7 +68,7 @@ static const struct named_register { } nonpriv_registers[] = { { "NOPID", NOCTX, RCS0, 0x2094 }, { "MI_PREDICATE_RESULT_2", NOCTX, RCS0, 0x23bc }, - { "INSTPM", GEN6, RCS0, 0x20c0, 1, BIT(8) /* ro counter */, true }, + { "INSTPM", GEN6, RCS0, 0x20c0, 1, BIT(8) /* ro counter */ | 0x9a20, true }, { "IA_VERTICES_COUNT", GEN4, RCS0, 0x2310, 2 }, { "IA_PRIMITIVES_COUNT", GEN4, RCS0, 0x2318, 2 }, { "VS_INVOCATION_COUNT", GEN4, RCS0, 0x2320, 2 }, @@ -78,7 +78,7 @@ static const struct named_register { { "GS_PRIMITIVES_COUNT", GEN4, RCS0, 0x2330, 2 }, { "CL_INVOCATION_COUNT", GEN4, RCS0, 0x2338, 2 }, { "CL_PRIMITIVES_COUNT", GEN4, RCS0, 0x2340, 2 }, - { "PS_INVOCATION_COUNT_0", GEN4, RCS0, 0x22c8, 2 }, + { "PS_INVOCATION_COUNT_0", GEN4, RCS0, 0x22c8, 2, .ignore_bits = 0x3 }, { "PS_DEPTH_COUNT_0", GEN4, RCS0, 0x22d8, 2 }, { "GPUGPU_DISPATCHDIMX", GEN8, RCS0, 0x2500 }, { "GPUGPU_DISPATCHDIMY", GEN8, RCS0, 0x2504 }, @@ -86,7 +86,7 @@ static const struct named_register { { "MI_PREDICATE_SRC0", GEN8, RCS0, 0x2400, 2 }, { "MI_PREDICATE_SRC1", GEN8, RCS0, 0x2408, 2 }, { "MI_PREDICATE_DATA", GEN8, RCS0, 0x2410, 2 }, - { "MI_PRED_RESULT", GEN8, RCS0, 0x2418 }, + { "MI_PRED_RESULT", GEN8, RCS0, 0x2418, .ignore_bits = ~1u }, { "3DPRIM_END_OFFSET", GEN6, RCS0, 0x2420 }, { "3DPRIM_START_VERTEX", GEN6, RCS0, 0x2430 }, { "3DPRIM_VERTEX_COUNT", GEN6, RCS0, 0x2434 }, @@ -94,20 +94,20 @@ static const struct named_register { { "3DPRIM_START_INSTANCE", GEN6, RCS0, 0x243c }, { "3DPRIM_BASE_VERTEX", GEN6, RCS0, 0x2440 }, { "GPGPU_THREADS_DISPATCHED", GEN8, RCS0, 0x2290, 2 }, - { "PS_INVOCATION_COUNT_1", GEN8, RCS0, 0x22f0, 2 }, + { "PS_INVOCATION_COUNT_1", GEN8, RCS0, 0x22f0, 2, .ignore_bits = 0x3 }, { "PS_DEPTH_COUNT_1", GEN8, RCS0, 0x22f8, 2 }, { "BB_OFFSET", GEN8, RCS0, 0x2158, .ignore_bits = 0x4 }, { "MI_PREDICATE_RESULT_1", GEN8, RCS0, 0x241c }, { "CS_GPR", GEN8, RCS0, 0x2600, 32 }, { "OA_CTX_CONTROL", GEN8, RCS0, 0x2360 }, { "OACTXID", GEN8, RCS0, 0x2364 }, - { "PS_INVOCATION_COUNT_2", GEN8, RCS0, 0x2448, 2 }, + { "PS_INVOCATION_COUNT_2", GEN8, RCS0, 0x2448, 2, .ignore_bits = 0x3 }, { "PS_DEPTH_COUNT_2", GEN8, RCS0, 0x2450, 2 }, - { "Cache_Mode_0", GEN7, RCS0, 0x7000 }, - { "Cache_Mode_1", GEN7, RCS0, 0x7004 }, - { "GT_MODE", GEN8, RCS0, 0x7008 }, + { "Cache_Mode_0", GEN7, RCS0, 0x7000, .masked = true }, + { "Cache_Mode_1", GEN7, RCS0, 0x7004, .masked = true }, + { "GT_MODE", GEN8, RCS0, 0x7008, .masked = true }, { "L3_Config", GEN7, RCS0, 0x7034 }, - { "TD_CTL", GEN8, RCS0, 0xe400 }, + { "TD_CTL", GEN8, RCS0, 0xe400, .masked = true }, { "TD_CTL2", GEN8, RCS0, 0xe404 }, { "SO_NUM_PRIMS_WRITEN0", GEN6, RCS0, 0x5200, 2 }, { "SO_NUM_PRIMS_WRITEN1", GEN6, RCS0, 0x5208, 2 }, @@ -117,22 +117,22 @@ static const struct named_register { { "SO_PRIM_STORAGE_NEEDED1", GEN6, RCS0, 0x5248, 2 }, { "SO_PRIM_STORAGE_NEEDED2", GEN6, RCS0, 0x5250, 2 }, { "SO_PRIM_STORAGE_NEEDED3", GEN6, RCS0, 0x5258, 2 }, - { "SO_WRITE_OFFSET0", GEN7, RCS0, 0x5280 }, - { "SO_WRITE_OFFSET1", GEN7, RCS0, 0x5284 }, - { "SO_WRITE_OFFSET2", GEN7, RCS0, 0x5288 }, - { "SO_WRITE_OFFSET3", GEN7, RCS0, 0x528c }, + { "SO_WRITE_OFFSET0", GEN7, RCS0, 0x5280, .ignore_bits = 0x3 }, + { "SO_WRITE_OFFSET1", GEN7, RCS0, 0x5284, .ignore_bits = 0x3 }, + { "SO_WRITE_OFFSET2", GEN7, RCS0, 0x5288, .ignore_bits = 0x3 }, + { "SO_WRITE_OFFSET3", GEN7, RCS0, 0x528c, .ignore_bits = 0x3 }, { "OA_CONTROL", NOCTX, RCS0, 0x2b00 }, { "PERF_CNT_1", NOCTX, RCS0, 0x91b8, 2 }, { "PERF_CNT_2", NOCTX, RCS0, 0x91c0, 2 }, /* Privileged (enabled by w/a + FORCE_TO_NONPRIV) */ { "CTX_PREEMPT", NOCTX /* GEN_RANGE(9, 10) */, RCS0, 0x2248 }, - { "CS_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x2580 }, - { "HDC_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x7304 }, - { "L3SQREG1", GEN8, RCS0, 0xb010 }, + { "CS_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x2580, .masked = true }, + { "HDC_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x7304, .masked = true }, + { "L3SQREG4", GEN9, RCS0, 0xb118, .ignore_bits = 0x1ffff0 }, { "BCS_GPR", GEN9, BCS0, 0x22600, 32 }, - { "BCS_SWCTRL", GEN8, BCS0, 0x22200 }, + { "BCS_SWCTRL", GEN8, BCS0, 0x22200, .masked = true }, { "VCS0_GPR", GEN9, VCS0, 0x12600, 32 }, { "MFC_VDBOX1", NOCTX, VCS0, 0x12800, 64 }, @@ -191,6 +191,45 @@ static bool ignore_register(uint32_t offset) return false; } +static uint32_t tmpl_regs(int fd, + uint32_t ctx, + const struct intel_execution_engine2 *e, + unsigned int flags, + uint32_t value) +{ + const unsigned int gen_bit = 1 << intel_gen(intel_get_drm_devid(fd)); + const unsigned int engine_bit = ENGINE(e->class, e->instance); + unsigned int regs_size; + uint32_t handle; + uint32_t *regs; + + regs_size = NUM_REGS * sizeof(uint32_t); + regs_size = PAGE_ALIGN(regs_size); + + handle = gem_create(fd, regs_size); + + regs = gem_mmap__cpu(fd, handle, 0, regs_size, PROT_WRITE); + gem_set_domain(fd, handle, + I915_GEM_DOMAIN_CPU, I915_GEM_DOMAIN_CPU); + + for (const struct named_register *r = nonpriv_registers; r->name; r++) { + if (!(r->engine_mask & engine_bit)) + continue; + if (!(r->gen_mask & gen_bit)) + continue; + for (unsigned count = r->count ?: 1, offset = r->offset; + count--; offset += 4) { + if (r->masked) + regs[offset/sizeof(*regs)] = value & 0xffff; + else + regs[offset/sizeof(*regs)] = value; + } + } + munmap(regs, regs_size); + + return handle; +} + static uint32_t read_regs(int fd, uint32_t ctx, const struct intel_execution_engine2 *e, @@ -474,6 +513,59 @@ static void compare_regs(int fd, uint32_t A, uint32_t B, const char *who) num_errors, who); } +static void nonpriv(int fd, + const struct intel_execution_engine2 *e, + unsigned int flags) +{ + static const uint32_t values[] = { + 0x0, + 0xffffffff, + 0xcccccccc, + 0x33333333, + 0x55555555, + 0xaaaaaaaa, + 0xdeadbeef + }; + unsigned int engine = + gem_class_instance_to_eb_flags(fd, e->class, e->instance); + unsigned int num_values = ARRAY_SIZE(values); + + gem_quiescent_gpu(fd); + + for (int v = 0; v < num_values; v++) { + igt_spin_t *spin = NULL; + uint32_t ctx, regs[2], tmpl; + + tmpl = tmpl_regs(fd, ctx, e, flags, values[v]); + + ctx = gem_context_create(fd); + regs[0] = read_regs(fd, ctx, e, flags); + + spin = igt_spin_batch_new(fd, .ctx = ctx, .engine = engine); + + igt_debug("%s[%d]: Setting all registers to 0x%08x\n", + __func__, v, values[v]); + write_regs(fd, ctx, e, flags, values[v]); + + regs[1] = read_regs(fd, ctx, e, flags); + + /* + * Restore the original register values before the HW idles. + * Or else it may never restart! + */ + restore_regs(fd, ctx, e, flags, regs[0]); + + igt_spin_batch_free(fd, spin); + + compare_regs(fd, tmpl, regs[1], "nonpriv read/writes"); + + for (int n = 0; n < ARRAY_SIZE(regs); n++) + gem_close(fd, regs[n]); + gem_context_destroy(fd, ctx); + gem_close(fd, tmpl); + } +} + static void isolation(int fd, const struct intel_execution_engine2 *e, unsigned int flags) @@ -715,6 +807,9 @@ igt_main igt_fork_hang_detector(fd); } + igt_subtest_f("%s-nonpriv", e->name) + nonpriv(fd, e, 0); + igt_subtest_f("%s-clean", e->name) isolation(fd, e, 0); igt_subtest_f("%s-dirty-create", e->name) diff --git a/tests/intel-ci/fast-feedback.testlist b/tests/intel-ci/fast-feedback.testlist index 2d22c2c1c..87eb8bbb9 100644 --- a/tests/intel-ci/fast-feedback.testlist +++ b/tests/intel-ci/fast-feedback.testlist @@ -12,6 +12,11 @@ igt@gem_close_race@basic-threads igt@gem_cpu_reloc@basic igt@gem_ctx_create@basic igt@gem_ctx_create@basic-files +igt@gem_ctx_isolation@rcs0-nonpriv +igt@gem_ctx_isolation@bcs0-nonpriv +igt@gem_ctx_isolation@vcs0-nonpriv +igt@gem_ctx_isolation@vcs1-nonpriv +igt@gem_ctx_isolation@vecs0-nonpriv igt@gem_ctx_exec@basic igt@gem_ctx_param@basic igt@gem_ctx_param@basic-default -- 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx