We need to support copying from one object backing store to another for
object migration.
Signed-off-by: Matthew Auld <matthew.auld@xxxxxxxxx>
Cc: Joonas Lahtinen <joonas.lahtinen@xxxxxxxxxxxxxxx>
Cc: Abdiel Janulgue <abdiel.janulgue@xxxxxxxxxxxxxxx>
---
drivers/gpu/drm/i915/i915_drv.h | 3 +
drivers/gpu/drm/i915/i915_gem.c | 187 ++++++++++++++++++
drivers/gpu/drm/i915/intel_gpu_commands.h | 2 +
.../gpu/drm/i915/selftests/i915_gem_object.c | 80 ++++++++
4 files changed, 272 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5b39af57c36c..b9d01caa3430 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2811,6 +2811,9 @@ void i915_gem_object_init(struct drm_i915_gem_object *obj,
const struct drm_i915_gem_object_ops *ops);
int i915_gem_object_clear_blt(struct i915_gem_context *ctx,
struct drm_i915_gem_object *obj);
+int i915_gem_object_copy_blt(struct i915_gem_context *ctx,
+ struct drm_i915_gem_object *src,
+ struct drm_i915_gem_object *dst);
struct drm_i915_gem_object *
i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size);
struct drm_i915_gem_object *
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 032d4334c0f1..501714fbf92f 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4288,6 +4288,193 @@ static bool discard_backing_storage(struct drm_i915_gem_object *obj)
return atomic_long_read(&obj->base.filp->f_count) == 1;
}
+static struct i915_vma *
+__i915_gem_copy_blt(struct i915_vma *src, struct i915_vma *dst)
+{
+ struct drm_i915_private *i915 = to_i915(src->obj->base.dev);
+ const int gen = INTEL_GEN(i915);
+ struct drm_i915_gem_object *obj;
+ struct i915_vma *batch;
+ u32 *cmd;
+ int err;
+
+ GEM_BUG_ON(src->vm != dst->vm);
+ GEM_BUG_ON(src->obj->base.size != dst->obj->base.size);
+
+ obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
+ if (IS_ERR(obj))
+ return ERR_CAST(obj);
+
+ cmd = i915_gem_object_pin_map(obj, I915_MAP_WB);
+ if (IS_ERR(cmd)) {
+ err = PTR_ERR(cmd);
+ goto err;
+ }
+
+ if (gen >= 9) {
+ *cmd++ = GEN9_XY_FAST_COPY_BLT_CMD;
+ *cmd++ = BLT_DEPTH_32 | PAGE_SIZE;
+ *cmd++ = 0;
+ *cmd++ = src->obj->base.size >> PAGE_SHIFT << 16 | PAGE_SIZE / 4;
+ *cmd++ = lower_32_bits(dst->node.start);
+ *cmd++ = upper_32_bits(dst->node.start);
+ *cmd++ = 0;
+ *cmd++ = PAGE_SIZE;
+ *cmd++ = lower_32_bits(src->node.start);
+ *cmd++ = upper_32_bits(src->node.start);
+ } else if (gen >= 8) {
+ *cmd++ = GEN8_XY_SRC_COPY_BLT_CMD | BLT_WRITE_RGBA;
+ *cmd++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | PAGE_SIZE;
+ *cmd++ = 0;
+ *cmd++ = src->obj->base.size >> PAGE_SHIFT << 16 | PAGE_SIZE / 4;
+ *cmd++ = lower_32_bits(dst->node.start);
+ *cmd++ = upper_32_bits(dst->node.start);
+ *cmd++ = 0;
+ *cmd++ = PAGE_SIZE;
+ *cmd++ = lower_32_bits(src->node.start);
+ *cmd++ = upper_32_bits(src->node.start);
+ } else {
+ *cmd++ = XY_SRC_COPY_BLT_CMD | BLT_WRITE_RGBA;
+ *cmd++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | PAGE_SIZE;
+ *cmd++ = 0;
+ *cmd++ = src->obj->base.size >> PAGE_SHIFT << 16 | PAGE_SIZE / 4;
+ *cmd++ = dst->node.start;
+ *cmd++ = 0;
+ *cmd++ = PAGE_SIZE;
+ *cmd++ = src->node.start;
+ }
+
+ *cmd = MI_BATCH_BUFFER_END;
+
+ i915_gem_object_unpin_map(obj);
+
+ err = i915_gem_object_set_to_gtt_domain(obj, false);
+ if (err)
+ goto err;
+
+ batch = i915_vma_instance(obj, src->vm, NULL);
+ if (IS_ERR(batch)) {
+ err = PTR_ERR(batch);
+ goto err;
+ }
+
+ err = i915_vma_pin(batch, 0, 0, PIN_USER);
+ if (err)
+ goto err;
+
+ return batch;
+
+err:
+ i915_gem_object_put(obj);
+ return ERR_PTR(err);
+}
+
+static int i915_gem_copy_blt(struct i915_gem_context *ctx,
+ struct i915_vma *src,
+ struct i915_vma *dst)
+{
+ struct drm_i915_private *i915 = to_i915(src->obj->base.dev);
+ struct intel_engine_cs *engine = i915->engine[BCS];
+ struct i915_request *rq;
+ struct i915_vma *batch;
+ int flags = 0;
+ int err;
+
+ err = i915_gem_object_set_to_gtt_domain(src->obj, false);
+ if (err)
+ return err;
+
+ err = i915_gem_object_set_to_gtt_domain(dst->obj, true);
+ if (err)
+ return err;
+
+ rq = i915_request_alloc(engine, ctx);
+ if (IS_ERR(rq))
+ return PTR_ERR(rq);
+
+ batch = __i915_gem_copy_blt(src, dst);
+ if (IS_ERR(batch)) {
+ err = PTR_ERR(batch);
+ goto err_request;
+ }
+
+ err = i915_vma_move_to_active(batch, rq, 0);
+ i915_vma_unpin(batch);
+ i915_vma_close(batch);
+ if (err) {
+ i915_gem_object_put(batch->obj);
+ goto err_request;
+ }
+
+ i915_gem_object_set_active_reference(batch->obj);
+
+ err = engine->emit_bb_start(rq,
+ batch->node.start, batch->node.size,
+ flags);
+ if (err)
+ goto err_request;
+
+ err = i915_vma_move_to_active(src, rq, 0);
+ if (err) {
+ i915_request_skip(rq, err);
+ goto err_request;
+ }
+
+ err = i915_vma_move_to_active(dst, rq, EXEC_OBJECT_WRITE);
+ if (err)
+ i915_request_skip(rq, err);
+
+err_request:
+ i915_request_add(rq);
+ return err;
+}
+
+int i915_gem_object_copy_blt(struct i915_gem_context *ctx,
+ struct drm_i915_gem_object *src,
+ struct drm_i915_gem_object *dst)
+{
+ struct drm_i915_private *i915 = to_i915(src->base.dev);
+ struct i915_address_space *vm = ctx->ppgtt ? &ctx->ppgtt->vm: &i915->ggtt.vm;
+ struct i915_vma *src_vma;
+ struct i915_vma *dst_vma;
+ int err;
+
+ lockdep_assert_held(&i915->drm.struct_mutex);
+
+ src_vma = i915_vma_instance(src, vm, NULL);
+ if (IS_ERR(src_vma))
+ return PTR_ERR(src_vma);
+
+ err = i915_vma_pin(src_vma, 0, 0, PIN_USER);
+ if (err)
+ return err;
+
+ dst_vma = i915_vma_instance(dst, vm, NULL);
+ if (IS_ERR(dst_vma)) {
+ err = PTR_ERR(dst_vma);
+ goto out_unpin_src;
+ }
+
+ err = i915_vma_pin(dst_vma, 0, 0, PIN_USER);
+ if (err)
+ goto out_unpin_src;
+
+ err = i915_gem_copy_blt(ctx, src_vma, dst_vma);
+ i915_vma_unpin(src_vma);
+ i915_vma_unpin(dst_vma);
+ if (err)
+ return err;
+
+ return i915_gem_object_wait(dst,
+ I915_WAIT_LOCKED |
+ I915_WAIT_ALL,
+ MAX_SCHEDULE_TIMEOUT);
+
+out_unpin_src:
+ i915_vma_unpin(src_vma);
+ return err;
+}
+
static struct i915_vma *
__i915_gem_fill_blt(struct i915_vma *vma, u32 value)
{
diff --git a/drivers/gpu/drm/i915/intel_gpu_commands.h b/drivers/gpu/drm/i915/intel_gpu_commands.h
index f74ff1d095c2..e97e9066676c 100644
--- a/drivers/gpu/drm/i915/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/intel_gpu_commands.h
@@ -178,6 +178,8 @@
#define XY_COLOR_BLT_CMD (2<<29 | 0x50<<22 | (7-2))
#define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)
#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
+#define GEN8_XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|8)
+#define GEN9_XY_FAST_COPY_BLT_CMD ((2<<29)|(0x42<<22)|8)
#define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5)
#define BLT_WRITE_A (2<<20)
#define BLT_WRITE_RGB (1<<20)
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_object.c b/drivers/gpu/drm/i915/selftests/i915_gem_object.c
index c83dc5e2f219..dabb03885899 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_object.c
@@ -697,6 +697,85 @@ static int igt_fill_blt(void *arg)
return err;
}
+static int igt_copy_blt(void *arg)
+{
+ struct drm_i915_private *i915 = arg;
+ struct drm_i915_gem_object *src, *dst;
+ struct i915_gem_context *ctx;
+ struct drm_file *file;
+ u32 *vaddr;
+ int err;
+ u32 i;
+
+ file = mock_file(i915);
+ if (IS_ERR(file))
+ return PTR_ERR(file);
+
+ ctx = live_context(i915, file);
+ if (IS_ERR(ctx)) {
+ err = PTR_ERR(ctx);
+ goto err_file;
+ }
+
+ src = i915_gem_object_create_internal(i915, SZ_2M);
+ if (IS_ERR(src)) {
+ err = PTR_ERR(src);
+ goto err_file;
+ }
+
+ vaddr = i915_gem_object_pin_map(src, I915_MAP_WB);
+ if (IS_ERR(vaddr)) {
+ err = PTR_ERR(vaddr);
+ goto err_put_src;
+ }
+
+ for (i = 0; i < src->base.size / sizeof(u32); ++i)
+ vaddr[i] = i;
+
+ i915_gem_object_unpin_map(src);
+
+ dst = i915_gem_object_create_internal(i915, SZ_2M);
+ if (IS_ERR(dst)) {
+ err = PTR_ERR(dst);
+ goto err_put_src;
+ }
+
+ mutex_lock(&i915->drm.struct_mutex);
+
+ err = i915_gem_object_copy_blt(ctx, src, dst);
+ if (err)
+ goto err_put_dst;
+
+ err = i915_gem_object_set_to_cpu_domain(dst, false);
+ if (err)
+ goto err_put_dst;
+
+ mutex_unlock(&i915->drm.struct_mutex);
+
+ vaddr = i915_gem_object_pin_map(dst, I915_MAP_WB);
+ if (IS_ERR(vaddr)) {
+ err = PTR_ERR(vaddr);
+ goto err_put_dst;
+ }
+
+ for (i = 0; i < dst->base.size / sizeof(u32); ++i) {
+ if (vaddr[i] != i) {
+ pr_err("vaddr[%d]=%u, expected=%u\n", i, vaddr[i], i);
+ err = -EINVAL;
+ break;
+ }
+ }
+
+ i915_gem_object_unpin_map(dst);
+err_put_dst:
+ i915_gem_object_put(dst);
+err_put_src:
+ i915_gem_object_put(src);
+err_file:
+ mock_file_free(i915, file);
+ return err;
+}
+
int i915_gem_object_mock_selftests(void)
{
static const struct i915_subtest tests[] = {
@@ -723,6 +802,7 @@ int i915_gem_object_live_selftests(struct drm_i915_private *i915)
SUBTEST(igt_partial_tiling),
SUBTEST(igt_mmap_offset_exhaustion),
SUBTEST(igt_fill_blt),
+ SUBTEST(igt_copy_blt),
};
return i915_subtests(tests, i915);
--
2.20.1
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