On Mon, Jan 28, 2019 at 02:00:12PM -0800, Aditya Swarup wrote:
> Macros to be organized semantically by dword, lane and
> port(in this order).
>
> Cc: Clint Taylor <clinton.a.taylor@xxxxxxxxx>
> Cc: Imre Deak <imre.deak@xxxxxxxxx>
> Cc: Jani Nikula <jani.nikula@xxxxxxxxxxxxxxx>
> Signed-off-by: Aditya Swarup <aditya.swarup@xxxxxxxxx>
Also please add Fixes tag with SHA of the original patch that
adds these macros.
With that,
Reviewed-by: Manasi navare <manasi.d.navare@xxxxxxxxx>
Manasi
> ---
> drivers/gpu/drm/i915/i915_reg.h | 50 ++++++++++++++++----------------
> drivers/gpu/drm/i915/intel_ddi.c | 44 ++++++++++++++--------------
> 2 files changed, 47 insertions(+), 47 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b0535073c3f0..da8fcdc456d2 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1897,7 +1897,7 @@ enum i915_power_well_id {
> #define N_SCALAR(x) ((x) << 24)
> #define N_SCALAR_MASK (0x7F << 24)
>
> -#define MG_PHY_PORT_LN(port, ln, ln0p1, ln0p2, ln1p1) \
> +#define MG_PHY_PORT_LN(ln, port, ln0p1, ln0p2, ln1p1) \
> _MMIO(_PORT((port) - PORT_C, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))
>
> #define MG_TX_LINK_PARAMS_TX1LN0_PORT1 0x16812C
> @@ -1908,8 +1908,8 @@ enum i915_power_well_id {
> #define MG_TX_LINK_PARAMS_TX1LN1_PORT3 0x16A52C
> #define MG_TX_LINK_PARAMS_TX1LN0_PORT4 0x16B12C
> #define MG_TX_LINK_PARAMS_TX1LN1_PORT4 0x16B52C
> -#define MG_TX1_LINK_PARAMS(port, ln) \
> - MG_PHY_PORT_LN(port, ln, MG_TX_LINK_PARAMS_TX1LN0_PORT1, \
> +#define MG_TX1_LINK_PARAMS(ln, port) \
> + MG_PHY_PORT_LN(ln, port, MG_TX_LINK_PARAMS_TX1LN0_PORT1, \
> MG_TX_LINK_PARAMS_TX1LN0_PORT2, \
> MG_TX_LINK_PARAMS_TX1LN1_PORT1)
>
> @@ -1921,8 +1921,8 @@ enum i915_power_well_id {
> #define MG_TX_LINK_PARAMS_TX2LN1_PORT3 0x16A4AC
> #define MG_TX_LINK_PARAMS_TX2LN0_PORT4 0x16B0AC
> #define MG_TX_LINK_PARAMS_TX2LN1_PORT4 0x16B4AC
> -#define MG_TX2_LINK_PARAMS(port, ln) \
> - MG_PHY_PORT_LN(port, ln, MG_TX_LINK_PARAMS_TX2LN0_PORT1, \
> +#define MG_TX2_LINK_PARAMS(ln, port) \
> + MG_PHY_PORT_LN(ln, port, MG_TX_LINK_PARAMS_TX2LN0_PORT1, \
> MG_TX_LINK_PARAMS_TX2LN0_PORT2, \
> MG_TX_LINK_PARAMS_TX2LN1_PORT1)
> #define CRI_USE_FS32 (1 << 5)
> @@ -1935,8 +1935,8 @@ enum i915_power_well_id {
> #define MG_TX_PISO_READLOAD_TX1LN1_PORT3 0x16A54C
> #define MG_TX_PISO_READLOAD_TX1LN0_PORT4 0x16B14C
> #define MG_TX_PISO_READLOAD_TX1LN1_PORT4 0x16B54C
> -#define MG_TX1_PISO_READLOAD(port, ln) \
> - MG_PHY_PORT_LN(port, ln, MG_TX_PISO_READLOAD_TX1LN0_PORT1, \
> +#define MG_TX1_PISO_READLOAD(ln, port) \
> + MG_PHY_PORT_LN(ln, port, MG_TX_PISO_READLOAD_TX1LN0_PORT1, \
> MG_TX_PISO_READLOAD_TX1LN0_PORT2, \
> MG_TX_PISO_READLOAD_TX1LN1_PORT1)
>
> @@ -1948,8 +1948,8 @@ enum i915_power_well_id {
> #define MG_TX_PISO_READLOAD_TX2LN1_PORT3 0x16A4CC
> #define MG_TX_PISO_READLOAD_TX2LN0_PORT4 0x16B0CC
> #define MG_TX_PISO_READLOAD_TX2LN1_PORT4 0x16B4CC
> -#define MG_TX2_PISO_READLOAD(port, ln) \
> - MG_PHY_PORT_LN(port, ln, MG_TX_PISO_READLOAD_TX2LN0_PORT1, \
> +#define MG_TX2_PISO_READLOAD(ln, port) \
> + MG_PHY_PORT_LN(ln, port, MG_TX_PISO_READLOAD_TX2LN0_PORT1, \
> MG_TX_PISO_READLOAD_TX2LN0_PORT2, \
> MG_TX_PISO_READLOAD_TX2LN1_PORT1)
> #define CRI_CALCINIT (1 << 1)
> @@ -1962,8 +1962,8 @@ enum i915_power_well_id {
> #define MG_TX_SWINGCTRL_TX1LN1_PORT3 0x16A548
> #define MG_TX_SWINGCTRL_TX1LN0_PORT4 0x16B148
> #define MG_TX_SWINGCTRL_TX1LN1_PORT4 0x16B548
> -#define MG_TX1_SWINGCTRL(port, ln) \
> - MG_PHY_PORT_LN(port, ln, MG_TX_SWINGCTRL_TX1LN0_PORT1, \
> +#define MG_TX1_SWINGCTRL(ln, port) \
> + MG_PHY_PORT_LN(ln, port, MG_TX_SWINGCTRL_TX1LN0_PORT1, \
> MG_TX_SWINGCTRL_TX1LN0_PORT2, \
> MG_TX_SWINGCTRL_TX1LN1_PORT1)
>
> @@ -1975,8 +1975,8 @@ enum i915_power_well_id {
> #define MG_TX_SWINGCTRL_TX2LN1_PORT3 0x16A4C8
> #define MG_TX_SWINGCTRL_TX2LN0_PORT4 0x16B0C8
> #define MG_TX_SWINGCTRL_TX2LN1_PORT4 0x16B4C8
> -#define MG_TX2_SWINGCTRL(port, ln) \
> - MG_PHY_PORT_LN(port, ln, MG_TX_SWINGCTRL_TX2LN0_PORT1, \
> +#define MG_TX2_SWINGCTRL(ln, port) \
> + MG_PHY_PORT_LN(ln, port, MG_TX_SWINGCTRL_TX2LN0_PORT1, \
> MG_TX_SWINGCTRL_TX2LN0_PORT2, \
> MG_TX_SWINGCTRL_TX2LN1_PORT1)
> #define CRI_TXDEEMPH_OVERRIDE_17_12(x) ((x) << 0)
> @@ -1990,8 +1990,8 @@ enum i915_power_well_id {
> #define MG_TX_DRVCTRL_TX1LN1_TXPORT3 0x16A544
> #define MG_TX_DRVCTRL_TX1LN0_TXPORT4 0x16B144
> #define MG_TX_DRVCTRL_TX1LN1_TXPORT4 0x16B544
> -#define MG_TX1_DRVCTRL(port, ln) \
> - MG_PHY_PORT_LN(port, ln, MG_TX_DRVCTRL_TX1LN0_TXPORT1, \
> +#define MG_TX1_DRVCTRL(ln, port) \
> + MG_PHY_PORT_LN(ln, port, MG_TX_DRVCTRL_TX1LN0_TXPORT1, \
> MG_TX_DRVCTRL_TX1LN0_TXPORT2, \
> MG_TX_DRVCTRL_TX1LN1_TXPORT1)
>
> @@ -2003,8 +2003,8 @@ enum i915_power_well_id {
> #define MG_TX_DRVCTRL_TX2LN1_PORT3 0x16A4C4
> #define MG_TX_DRVCTRL_TX2LN0_PORT4 0x16B0C4
> #define MG_TX_DRVCTRL_TX2LN1_PORT4 0x16B4C4
> -#define MG_TX2_DRVCTRL(port, ln) \
> - MG_PHY_PORT_LN(port, ln, MG_TX_DRVCTRL_TX2LN0_PORT1, \
> +#define MG_TX2_DRVCTRL(ln, port) \
> + MG_PHY_PORT_LN(ln, port, MG_TX_DRVCTRL_TX2LN0_PORT1, \
> MG_TX_DRVCTRL_TX2LN0_PORT2, \
> MG_TX_DRVCTRL_TX2LN1_PORT1)
> #define CRI_TXDEEMPH_OVERRIDE_11_6(x) ((x) << 24)
> @@ -2023,8 +2023,8 @@ enum i915_power_well_id {
> #define MG_CLKHUB_LN1_PORT3 0x16A79C
> #define MG_CLKHUB_LN0_PORT4 0x16B39C
> #define MG_CLKHUB_LN1_PORT4 0x16B79C
> -#define MG_CLKHUB(port, ln) \
> - MG_PHY_PORT_LN(port, ln, MG_CLKHUB_LN0_PORT1, \
> +#define MG_CLKHUB(ln, port) \
> + MG_PHY_PORT_LN(ln, port, MG_CLKHUB_LN0_PORT1, \
> MG_CLKHUB_LN0_PORT2, \
> MG_CLKHUB_LN1_PORT1)
> #define CFG_LOW_RATE_LKREN_EN (1 << 11)
> @@ -2037,8 +2037,8 @@ enum i915_power_well_id {
> #define MG_TX_DCC_TX1LN1_PORT3 0x16A510
> #define MG_TX_DCC_TX1LN0_PORT4 0x16B110
> #define MG_TX_DCC_TX1LN1_PORT4 0x16B510
> -#define MG_TX1_DCC(port, ln) \
> - MG_PHY_PORT_LN(port, ln, MG_TX_DCC_TX1LN0_PORT1, \
> +#define MG_TX1_DCC(ln, port) \
> + MG_PHY_PORT_LN(ln, port, MG_TX_DCC_TX1LN0_PORT1, \
> MG_TX_DCC_TX1LN0_PORT2, \
> MG_TX_DCC_TX1LN1_PORT1)
> #define MG_TX_DCC_TX2LN0_PORT1 0x168090
> @@ -2049,8 +2049,8 @@ enum i915_power_well_id {
> #define MG_TX_DCC_TX2LN1_PORT3 0x16A490
> #define MG_TX_DCC_TX2LN0_PORT4 0x16B090
> #define MG_TX_DCC_TX2LN1_PORT4 0x16B490
> -#define MG_TX2_DCC(port, ln) \
> - MG_PHY_PORT_LN(port, ln, MG_TX_DCC_TX2LN0_PORT1, \
> +#define MG_TX2_DCC(ln, port) \
> + MG_PHY_PORT_LN(ln, port, MG_TX_DCC_TX2LN0_PORT1, \
> MG_TX_DCC_TX2LN0_PORT2, \
> MG_TX_DCC_TX2LN1_PORT1)
> #define CFG_AMI_CK_DIV_OVERRIDE_VAL(x) ((x) << 25)
> @@ -2065,8 +2065,8 @@ enum i915_power_well_id {
> #define MG_DP_MODE_LN1_ACU_PORT3 0x16A7A0
> #define MG_DP_MODE_LN0_ACU_PORT4 0x16B3A0
> #define MG_DP_MODE_LN1_ACU_PORT4 0x16B7A0
> -#define MG_DP_MODE(port, ln) \
> - MG_PHY_PORT_LN(port, ln, MG_DP_MODE_LN0_ACU_PORT1, \
> +#define MG_DP_MODE(ln, port) \
> + MG_PHY_PORT_LN(ln, port, MG_DP_MODE_LN0_ACU_PORT1, \
> MG_DP_MODE_LN0_ACU_PORT2, \
> MG_DP_MODE_LN1_ACU_PORT1)
> #define MG_DP_MODE_CFG_DP_X2_MODE (1 << 7)
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index c6def69348a6..32d42f2dc3d1 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2553,33 +2553,33 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
>
> /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */
> for (ln = 0; ln < 2; ln++) {
> - val = I915_READ(MG_TX1_LINK_PARAMS(port, ln));
> + val = I915_READ(MG_TX1_LINK_PARAMS(ln, port));
> val &= ~CRI_USE_FS32;
> - I915_WRITE(MG_TX1_LINK_PARAMS(port, ln), val);
> + I915_WRITE(MG_TX1_LINK_PARAMS(ln, port), val);
>
> - val = I915_READ(MG_TX2_LINK_PARAMS(port, ln));
> + val = I915_READ(MG_TX2_LINK_PARAMS(ln, port));
> val &= ~CRI_USE_FS32;
> - I915_WRITE(MG_TX2_LINK_PARAMS(port, ln), val);
> + I915_WRITE(MG_TX2_LINK_PARAMS(ln, port), val);
> }
>
> /* Program MG_TX_SWINGCTRL with values from vswing table */
> for (ln = 0; ln < 2; ln++) {
> - val = I915_READ(MG_TX1_SWINGCTRL(port, ln));
> + val = I915_READ(MG_TX1_SWINGCTRL(ln, port));
> val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
> val |= CRI_TXDEEMPH_OVERRIDE_17_12(
> ddi_translations[level].cri_txdeemph_override_17_12);
> - I915_WRITE(MG_TX1_SWINGCTRL(port, ln), val);
> + I915_WRITE(MG_TX1_SWINGCTRL(ln, port), val);
>
> - val = I915_READ(MG_TX2_SWINGCTRL(port, ln));
> + val = I915_READ(MG_TX2_SWINGCTRL(ln, port));
> val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
> val |= CRI_TXDEEMPH_OVERRIDE_17_12(
> ddi_translations[level].cri_txdeemph_override_17_12);
> - I915_WRITE(MG_TX2_SWINGCTRL(port, ln), val);
> + I915_WRITE(MG_TX2_SWINGCTRL(ln, port), val);
> }
>
> /* Program MG_TX_DRVCTRL with values from vswing table */
> for (ln = 0; ln < 2; ln++) {
> - val = I915_READ(MG_TX1_DRVCTRL(port, ln));
> + val = I915_READ(MG_TX1_DRVCTRL(ln, port));
> val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
> CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
> val |= CRI_TXDEEMPH_OVERRIDE_5_0(
> @@ -2587,9 +2587,9 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
> CRI_TXDEEMPH_OVERRIDE_11_6(
> ddi_translations[level].cri_txdeemph_override_11_6) |
> CRI_TXDEEMPH_OVERRIDE_EN;
> - I915_WRITE(MG_TX1_DRVCTRL(port, ln), val);
> + I915_WRITE(MG_TX1_DRVCTRL(ln, port), val);
>
> - val = I915_READ(MG_TX2_DRVCTRL(port, ln));
> + val = I915_READ(MG_TX2_DRVCTRL(ln, port));
> val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
> CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
> val |= CRI_TXDEEMPH_OVERRIDE_5_0(
> @@ -2597,7 +2597,7 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
> CRI_TXDEEMPH_OVERRIDE_11_6(
> ddi_translations[level].cri_txdeemph_override_11_6) |
> CRI_TXDEEMPH_OVERRIDE_EN;
> - I915_WRITE(MG_TX2_DRVCTRL(port, ln), val);
> + I915_WRITE(MG_TX2_DRVCTRL(ln, port), val);
>
> /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */
> }
> @@ -2608,17 +2608,17 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
> * values from table for which TX1 and TX2 enabled.
> */
> for (ln = 0; ln < 2; ln++) {
> - val = I915_READ(MG_CLKHUB(port, ln));
> + val = I915_READ(MG_CLKHUB(ln, port));
> if (link_clock < 300000)
> val |= CFG_LOW_RATE_LKREN_EN;
> else
> val &= ~CFG_LOW_RATE_LKREN_EN;
> - I915_WRITE(MG_CLKHUB(port, ln), val);
> + I915_WRITE(MG_CLKHUB(ln, port), val);
> }
>
> /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */
> for (ln = 0; ln < 2; ln++) {
> - val = I915_READ(MG_TX1_DCC(port, ln));
> + val = I915_READ(MG_TX1_DCC(ln, port));
> val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
> if (link_clock <= 500000) {
> val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
> @@ -2626,9 +2626,9 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
> val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
> CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
> }
> - I915_WRITE(MG_TX1_DCC(port, ln), val);
> + I915_WRITE(MG_TX1_DCC(ln, port), val);
>
> - val = I915_READ(MG_TX2_DCC(port, ln));
> + val = I915_READ(MG_TX2_DCC(ln, port));
> val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
> if (link_clock <= 500000) {
> val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
> @@ -2636,18 +2636,18 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
> val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
> CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
> }
> - I915_WRITE(MG_TX2_DCC(port, ln), val);
> + I915_WRITE(MG_TX2_DCC(ln, port), val);
> }
>
> /* Program MG_TX_PISO_READLOAD with values from vswing table */
> for (ln = 0; ln < 2; ln++) {
> - val = I915_READ(MG_TX1_PISO_READLOAD(port, ln));
> + val = I915_READ(MG_TX1_PISO_READLOAD(ln, port));
> val |= CRI_CALCINIT;
> - I915_WRITE(MG_TX1_PISO_READLOAD(port, ln), val);
> + I915_WRITE(MG_TX1_PISO_READLOAD(ln, port), val);
>
> - val = I915_READ(MG_TX2_PISO_READLOAD(port, ln));
> + val = I915_READ(MG_TX2_PISO_READLOAD(ln, port));
> val |= CRI_CALCINIT;
> - I915_WRITE(MG_TX2_PISO_READLOAD(port, ln), val);
> + I915_WRITE(MG_TX2_PISO_READLOAD(ln, port), val);
> }
> }
>
> --
> 2.17.1
>
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