== Series Details == Series: Enable/disable gamma/csc dynamically and fix C8 (rev2) URL : https://patchwork.freedesktop.org/series/55081/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Split the gamma/csc enable bits from the plane_ctl() function Okay! Commit: drm/i915: Precompute gamma_mode Okay! Commit: drm/i915: Constify the state arguments to the color management stuff Okay! Commit: drm/i915: Pull GAMMA_MODE write out from haswell_load_luts() Okay! Commit: drm/i915: Split color mgmt based on single vs. double buffered registers -drivers/gpu/drm/i915/selftests/../i915_drv.h:3565:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3577:16: warning: expression using sizeof(void) Commit: drm/i915: Move LUT programming to happen after vblank waits Okay! Commit: drm/i915: Populate gamma_mode for all platforms Okay! Commit: drm/i915: Track pipe gamma enable/disable in crtc state Okay! Commit: drm/i915: Track pipe csc enable in crtc state Okay! Commit: drm/i915: Turn off pipe gamma when it's not needed Okay! Commit: drm/i915: Turn off pipe CSC when it's not needed Okay! Commit: drm/i915: Disable pipe gamma when C8 pixel format is used Okay! Commit: drm/i915: Update DSPCNTR gamma/csc bits during crtc_enable() Okay! _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
