On Sat, Feb 02, 2019 at 12:09:47AM +0000, Souza, Jose wrote:
> On Fri, 2019-02-01 at 15:50 -0800, Rodrigo Vivi wrote:
> > While cross checking PCI IDs from Intel Media SDK
> > and kernel Dmitry noticed this gap. So we checked the
> > spec and this new ID had been recently added.
> >
> > v2: Adding new H_GT1 entry to i915_pci.c (Jose)
> >
>
> Reviewed-by: José Roberto de Souza <jose.souza@xxxxxxxxx>
pushed, thanks.
>
> > Reported-by: Dmitry Rogozhkin<dmitry.v.rogozhkin@xxxxxxxxx>
> > Cc: Dmitry Rogozhkin<dmitry.v.rogozhkin@xxxxxxxxx>
> > Cc: José Roberto de Souza <jose.souza@xxxxxxxxx>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
> > ---
> > drivers/gpu/drm/i915/i915_pci.c | 1 +
> > include/drm/i915_pciids.h | 4 ++++
> > 2 files changed, 5 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_pci.c
> > b/drivers/gpu/drm/i915/i915_pci.c
> > index 17f5a605b0b3..5d05572c9ff4 100644
> > --- a/drivers/gpu/drm/i915/i915_pci.c
> > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > @@ -713,6 +713,7 @@ static const struct pci_device_id pciidlist[] = {
> > INTEL_AML_KBL_GT2_IDS(&intel_kabylake_gt2_info),
> > INTEL_CFL_S_GT1_IDS(&intel_coffeelake_gt1_info),
> > INTEL_CFL_S_GT2_IDS(&intel_coffeelake_gt2_info),
> > + INTEL_CFL_H_GT1_IDS(&intel_coffeelake_gt1_info),
> > INTEL_CFL_H_GT2_IDS(&intel_coffeelake_gt2_info),
> > INTEL_CFL_U_GT2_IDS(&intel_coffeelake_gt2_info),
> > INTEL_CFL_U_GT3_IDS(&intel_coffeelake_gt3_info),
> > diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> > index df72be7e8b88..d2fad7b0fcf6 100644
> > --- a/include/drm/i915_pciids.h
> > +++ b/include/drm/i915_pciids.h
> > @@ -394,6 +394,9 @@
> > INTEL_VGA_DEVICE(0x3E9A, info) /* SRV GT2 */
> >
> > /* CFL H */
> > +#define INTEL_CFL_H_GT1_IDS(info) \
> > + INTEL_VGA_DEVICE(0x3E9C, info)
> > +
> > #define INTEL_CFL_H_GT2_IDS(info) \
> > INTEL_VGA_DEVICE(0x3E9B, info), /* Halo GT2 */ \
> > INTEL_VGA_DEVICE(0x3E94, info) /* Halo GT2 */
> > @@ -426,6 +429,7 @@
> > #define INTEL_CFL_IDS(info) \
> > INTEL_CFL_S_GT1_IDS(info), \
> > INTEL_CFL_S_GT2_IDS(info), \
> > + INTEL_CFL_H_GT1_IDS(info), \
> > INTEL_CFL_H_GT2_IDS(info), \
> > INTEL_CFL_U_GT2_IDS(info), \
> > INTEL_CFL_U_GT3_IDS(info), \
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