Quoting Mika Kuoppala (2019-01-30 14:13:57) > Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> writes: > > > Actually measure how many batches we can fit into a ring before > > blocking, or else we may end up hanging the device earlier than > > expected! > > > > Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> > > Cc: Mika Kuoppala <mika.kuoppala@xxxxxxxxx> > > --- > > tests/i915/gem_eio.c | 19 +++++++++++++++---- > > 1 file changed, 15 insertions(+), 4 deletions(-) > > > > diff --git a/tests/i915/gem_eio.c b/tests/i915/gem_eio.c > > index 09059c311..534bd1899 100644 > > --- a/tests/i915/gem_eio.c > > +++ b/tests/i915/gem_eio.c > > @@ -44,6 +44,7 @@ > > #include "igt_device.h" > > #include "igt_sysfs.h" > > #include "sw_sync.h" > > +#include "i915/gem_ring.h" > > > > IGT_TEST_DESCRIPTION("Test that specific ioctls report a wedged GPU (EIO)."); > > > > @@ -358,10 +359,15 @@ static void test_inflight(int fd, unsigned int wait) > > { > > int parent_fd = fd; > > unsigned int engine; > > + int max; > > > > igt_require_gem(fd); > > igt_require(gem_has_exec_fence(fd)); > > > > + max = gem_measure_ring_inflight(fd, -1, 0); > > + igt_require(max > 1); > > + max = min(max - 1, 64); > > + > > for_each_engine(parent_fd, engine) { > > const uint32_t bbe = MI_BATCH_BUFFER_END; > > struct drm_i915_gem_exec_object2 obj[2]; > > @@ -389,7 +395,7 @@ static void test_inflight(int fd, unsigned int wait) > > execbuf.buffer_count = 2; > > execbuf.flags = engine | I915_EXEC_FENCE_OUT; > > > > - for (unsigned int n = 0; n < ARRAY_SIZE(fence); n++) { > > Move the fence array to upper scope and use that in finding the > max. As bonus you can remove the comment on 'conservative estimate of > ring size' as apparently we weren't so convervative after all. > > > Bugzilla ref or how did you noticed this? much hairpulling > potential this has. Just recent changes to bsw. I think there's a bugzilla for it, but will have to trawl. It's just solitary failure; the device is reset before the next igt (just not subtest). -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx