On Wed, Jan 16, 2019 at 09:51:33PM +0530, Uma Shankar wrote:
> Fixed the glk degamma lut programming which currently
> was hard coding a linear lut all the time, making degamma
> block of glk basically a pass through.
>
> Currently degamma lut for glk is assigned as 0 in platform
> configuration. Updated the same to 33 as per the hardware
> capability. IGT tests for degamma were getting skipped due to
> this, spotted by Swati.
>
> ToDo: The current gamma/degamm lut ABI has just 16bit for each
> color component. This is not enough for GLK+, since input
> precision is increased to 3.16 which will need 19bit entries.
>
> Credits-to: Swati Sharma <swati2.sharma@xxxxxxxxx>
> Signed-off-by: Uma Shankar <uma.shankar@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_pci.c | 2 +-
> drivers/gpu/drm/i915/intel_color.c | 36 ++++++++++++++++++++++++++++--------
> 2 files changed, 29 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index dd4aff2..24248d0 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -69,7 +69,7 @@
> #define CHV_COLORS \
> .color = { .degamma_lut_size = 65, .gamma_lut_size = 257 }
> #define GLK_COLORS \
> - .color = { .degamma_lut_size = 0, .gamma_lut_size = 1024 }
> + .color = { .degamma_lut_size = 33, .gamma_lut_size = 1024 }
>
> /* Keep in gen based order, and chronological order within a gen */
>
> diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
> index 37fd9dd..3712bd0 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -491,7 +491,7 @@ static void glk_load_degamma_lut(struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> enum pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
> - const uint32_t lut_size = 33;
> + const uint32_t lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
> uint32_t i;
>
> /*
> @@ -502,14 +502,34 @@ static void glk_load_degamma_lut(struct intel_crtc_state *crtc_state)
> I915_WRITE(PRE_CSC_GAMC_INDEX(pipe), 0);
> I915_WRITE(PRE_CSC_GAMC_INDEX(pipe), PRE_CSC_GAMC_AUTO_INCREMENT);
>
> - /*
> - * FIXME: The pipe degamma table in geminilake doesn't support
> - * different values per channel, so this just loads a linear table.
> - */
> - for (i = 0; i < lut_size; i++) {
> - uint32_t v = (i * (1 << 16)) / (lut_size - 1);
>
> - I915_WRITE(PRE_CSC_GAMC_DATA(pipe), v);
> + if (crtc_state->base.degamma_lut) {
> + struct drm_color_lut *lut = crtc_state->base.degamma_lut->data;
> +
> + for (i = 0; i < lut_size; i++) {
> + /*
> + * First 33 entries represent range from 0 to 1.0
> + * 34th and 35th entry will represent extended range
> + * inputs 3.0 and 7.0 respectively, currently clamped
> + * at 1.0. Since the precision is 16bit, the user
> + * value can be directly filled to register.
> + * The pipe degamma table in GLK+ onwards doesn't
> + * support different values per channel, so this just
> + * programs green value which will be equal to Red and
> + * Blue into the lut registers.
> + * ToDo: Extend to max 7.0. Enable 32 bit input value
> + * as compared to just 16 to achieve this.
> + */
> + I915_WRITE(PRE_CSC_GAMC_DATA(pipe), lut[i].green);
> + I915_WRITE(PRE_CSC_GAMC_DATA(pipe), lut[i].green);
I don't think the double-write here was intentional (and would probably
cause more problems than usual due to the index auto increment).
Other than that,
Reviewed-by: Matt Roper <matthew.d.roper@xxxxxxxxx>
> + }
> + } else {
> + /* load a linear table. */
> + for (i = 0; i < lut_size; i++) {
> + uint32_t v = (i * (1 << 16)) / (lut_size - 1);
> +
> + I915_WRITE(PRE_CSC_GAMC_DATA(pipe), v);
> + }
> }
>
> /* Clamp values > 1.0. */
> --
> 1.9.1
>
--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
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