Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> writes:
> Now that we know we measure the size of the engine->emit_breadcrumb()
> correctly, we can remove the previous manual counting.
>
> Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_request.c | 4 ++--
> drivers/gpu/drm/i915/intel_engine_cs.c | 7 +++----
> drivers/gpu/drm/i915/intel_lrc.c | 4 ----
> drivers/gpu/drm/i915/intel_ringbuffer.c | 28 +++++--------------------
> drivers/gpu/drm/i915/intel_ringbuffer.h | 2 +-
> 5 files changed, 11 insertions(+), 34 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c
> index f941e40fd373..ddc35e9dc0c0 100644
> --- a/drivers/gpu/drm/i915/i915_request.c
> +++ b/drivers/gpu/drm/i915/i915_request.c
> @@ -650,7 +650,7 @@ i915_request_alloc(struct intel_engine_cs *engine, struct i915_gem_context *ctx)
> * around inside i915_request_add() there is sufficient space at
> * the beginning of the ring as well.
> */
> - rq->reserved_space = 2 * engine->emit_breadcrumb_sz * sizeof(u32);
> + rq->reserved_space = 2 * engine->emit_breadcrumb_dw * sizeof(u32);
*_sz got me startled, raising doubts about the previous patch.
But it was misnamed all the way.
Obviously merge the previous patch before this one :)
Reviewed-by: Mika Kuoppala <mika.kuoppala@xxxxxxxxxxxxxxx>
>
> /*
> * Record the position of the start of the request so that
> @@ -901,7 +901,7 @@ void i915_request_add(struct i915_request *request)
> * GPU processing the request, we never over-estimate the
> * position of the ring's HEAD.
> */
> - cs = intel_ring_begin(request, engine->emit_breadcrumb_sz);
> + cs = intel_ring_begin(request, engine->emit_breadcrumb_dw);
> GEM_BUG_ON(IS_ERR(cs));
> request->postfix = intel_ring_offset(request, cs);
>
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index 883ba208d1c2..235a2d70d671 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -611,7 +611,7 @@ struct measure_breadcrumb {
> u32 cs[1024];
> };
>
> -static int measure_breadcrumb_sz(struct intel_engine_cs *engine)
> +static int measure_breadcrumb_dw(struct intel_engine_cs *engine)
> {
> struct measure_breadcrumb *frame;
> unsigned int dw;
> @@ -637,7 +637,6 @@ static int measure_breadcrumb_sz(struct intel_engine_cs *engine)
> frame->rq.timeline = &frame->timeline;
>
> dw = engine->emit_breadcrumb(&frame->rq, frame->cs) - frame->cs;
> - GEM_BUG_ON(dw != engine->emit_breadcrumb_sz);
>
> i915_timeline_fini(&frame->timeline);
> kfree(frame);
> @@ -698,11 +697,11 @@ int intel_engine_init_common(struct intel_engine_cs *engine)
> if (ret)
> goto err_breadcrumbs;
>
> - ret = measure_breadcrumb_sz(engine);
> + ret = measure_breadcrumb_dw(engine);
> if (ret < 0)
> goto err_status_page;
>
> - engine->emit_breadcrumb_sz = ret;
> + engine->emit_breadcrumb_dw = ret;
>
> return 0;
>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index d2299425cf2f..5551dd2ec0e6 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -2075,7 +2075,6 @@ static u32 *gen8_emit_breadcrumb(struct i915_request *request, u32 *cs)
>
> return gen8_emit_wa_tail(request, cs);
> }
> -static const int gen8_emit_breadcrumb_sz = 6 + WA_TAIL_DWORDS;
>
> static u32 *gen8_emit_breadcrumb_rcs(struct i915_request *request, u32 *cs)
> {
> @@ -2099,7 +2098,6 @@ static u32 *gen8_emit_breadcrumb_rcs(struct i915_request *request, u32 *cs)
>
> return gen8_emit_wa_tail(request, cs);
> }
> -static const int gen8_emit_breadcrumb_rcs_sz = 8 + WA_TAIL_DWORDS;
>
> static int gen8_init_rcs_context(struct i915_request *rq)
> {
> @@ -2192,7 +2190,6 @@ logical_ring_default_vfuncs(struct intel_engine_cs *engine)
>
> engine->emit_flush = gen8_emit_flush;
> engine->emit_breadcrumb = gen8_emit_breadcrumb;
> - engine->emit_breadcrumb_sz = gen8_emit_breadcrumb_sz;
>
> engine->set_default_submission = intel_execlists_set_default_submission;
>
> @@ -2298,7 +2295,6 @@ int logical_render_ring_init(struct intel_engine_cs *engine)
> engine->init_context = gen8_init_rcs_context;
> engine->emit_flush = gen8_emit_flush_render;
> engine->emit_breadcrumb = gen8_emit_breadcrumb_rcs;
> - engine->emit_breadcrumb_sz = gen8_emit_breadcrumb_rcs_sz;
>
> ret = logical_ring_init(engine);
> if (ret)
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 107c4934e2fa..09c90475168a 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -330,7 +330,6 @@ static u32 *gen6_rcs_emit_breadcrumb(struct i915_request *rq, u32 *cs)
>
> return cs;
> }
> -static const int gen6_rcs_emit_breadcrumb_sz = 14;
>
> static int
> gen7_render_ring_cs_stall_wa(struct i915_request *rq)
> @@ -432,7 +431,6 @@ static u32 *gen7_rcs_emit_breadcrumb(struct i915_request *rq, u32 *cs)
>
> return cs;
> }
> -static const int gen7_rcs_emit_breadcrumb_sz = 6;
>
> static u32 *gen6_xcs_emit_breadcrumb(struct i915_request *rq, u32 *cs)
> {
> @@ -446,7 +444,6 @@ static u32 *gen6_xcs_emit_breadcrumb(struct i915_request *rq, u32 *cs)
>
> return cs;
> }
> -static const int gen6_xcs_emit_breadcrumb_sz = 4;
>
> #define GEN7_XCS_WA 32
> static u32 *gen7_xcs_emit_breadcrumb(struct i915_request *rq, u32 *cs)
> @@ -475,7 +472,6 @@ static u32 *gen7_xcs_emit_breadcrumb(struct i915_request *rq, u32 *cs)
>
> return cs;
> }
> -static const int gen7_xcs_emit_breadcrumb_sz = 8 + GEN7_XCS_WA * 3;
> #undef GEN7_XCS_WA
>
> static void set_hwstam(struct intel_engine_cs *engine, u32 mask)
> @@ -885,7 +881,6 @@ static u32 *i9xx_emit_breadcrumb(struct i915_request *rq, u32 *cs)
>
> return cs;
> }
> -static const int i9xx_emit_breadcrumb_sz = 6;
>
> #define GEN5_WA_STORES 8 /* must be at least 1! */
> static u32 *gen5_emit_breadcrumb(struct i915_request *rq, u32 *cs)
> @@ -908,7 +903,6 @@ static u32 *gen5_emit_breadcrumb(struct i915_request *rq, u32 *cs)
>
> return cs;
> }
> -static const int gen5_emit_breadcrumb_sz = GEN5_WA_STORES * 3 + 2;
> #undef GEN5_WA_STORES
>
> static void
> @@ -2206,11 +2200,8 @@ static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv,
> engine->request_alloc = ring_request_alloc;
>
> engine->emit_breadcrumb = i9xx_emit_breadcrumb;
> - engine->emit_breadcrumb_sz = i9xx_emit_breadcrumb_sz;
> - if (IS_GEN(dev_priv, 5)) {
> + if (IS_GEN(dev_priv, 5))
> engine->emit_breadcrumb = gen5_emit_breadcrumb;
> - engine->emit_breadcrumb_sz = gen5_emit_breadcrumb_sz;
> - }
>
> engine->set_default_submission = i9xx_set_default_submission;
>
> @@ -2240,12 +2231,10 @@ int intel_init_render_ring_buffer(struct intel_engine_cs *engine)
> engine->init_context = intel_rcs_ctx_init;
> engine->emit_flush = gen7_render_ring_flush;
> engine->emit_breadcrumb = gen7_rcs_emit_breadcrumb;
> - engine->emit_breadcrumb_sz = gen7_rcs_emit_breadcrumb_sz;
> } else if (IS_GEN(dev_priv, 6)) {
> engine->init_context = intel_rcs_ctx_init;
> engine->emit_flush = gen6_render_ring_flush;
> engine->emit_breadcrumb = gen6_rcs_emit_breadcrumb;
> - engine->emit_breadcrumb_sz = gen6_rcs_emit_breadcrumb_sz;
> } else if (IS_GEN(dev_priv, 5)) {
> engine->emit_flush = gen4_render_ring_flush;
> } else {
> @@ -2281,13 +2270,10 @@ int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine)
> engine->emit_flush = gen6_bsd_ring_flush;
> engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;
>
> - if (IS_GEN(dev_priv, 6)) {
> + if (IS_GEN(dev_priv, 6))
> engine->emit_breadcrumb = gen6_xcs_emit_breadcrumb;
> - engine->emit_breadcrumb_sz = gen6_xcs_emit_breadcrumb_sz;
> - } else {
> + else
> engine->emit_breadcrumb = gen7_xcs_emit_breadcrumb;
> - engine->emit_breadcrumb_sz = gen7_xcs_emit_breadcrumb_sz;
> - }
> } else {
> engine->emit_flush = bsd_ring_flush;
> if (IS_GEN(dev_priv, 5))
> @@ -2310,13 +2296,10 @@ int intel_init_blt_ring_buffer(struct intel_engine_cs *engine)
> engine->emit_flush = gen6_ring_flush;
> engine->irq_enable_mask = GT_BLT_USER_INTERRUPT;
>
> - if (IS_GEN(dev_priv, 6)) {
> + if (IS_GEN(dev_priv, 6))
> engine->emit_breadcrumb = gen6_xcs_emit_breadcrumb;
> - engine->emit_breadcrumb_sz = gen6_xcs_emit_breadcrumb_sz;
> - } else {
> + else
> engine->emit_breadcrumb = gen7_xcs_emit_breadcrumb;
> - engine->emit_breadcrumb_sz = gen7_xcs_emit_breadcrumb_sz;
> - }
>
> return intel_init_ring_buffer(engine);
> }
> @@ -2335,7 +2318,6 @@ int intel_init_vebox_ring_buffer(struct intel_engine_cs *engine)
> engine->irq_disable = hsw_vebox_irq_disable;
>
> engine->emit_breadcrumb = gen7_xcs_emit_breadcrumb;
> - engine->emit_breadcrumb_sz = gen7_xcs_emit_breadcrumb_sz;
>
> return intel_init_ring_buffer(engine);
> }
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index 479bd53d4ac6..0834e91d4ace 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -471,7 +471,7 @@ struct intel_engine_cs {
> #define I915_DISPATCH_SECURE BIT(0)
> #define I915_DISPATCH_PINNED BIT(1)
> u32 *(*emit_breadcrumb)(struct i915_request *rq, u32 *cs);
> - int emit_breadcrumb_sz;
> + int emit_breadcrumb_dw;
>
> /* Pass the request to the hardware queue (e.g. directly into
> * the legacy ringbuffer or to the end of an execlist).
> --
> 2.20.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
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