On Mon, 2019-01-07 at 11:58 +0000, Tvrtko Ursulin wrote: [snip] > > > > > > static void gen8_gt_irq_ack(struct drm_i915_private *i915, > > @@ -3329,7 +3332,7 @@ void i915_handle_error(struct > > drm_i915_private *dev_priv, > > if (intel_has_reset_engine(dev_priv) && > > !i915_terminally_wedged(&dev_priv->gpu_error)) { > > for_each_engine_masked(engine, dev_priv, engine_mask, > > tmp) { > > - BUILD_BUG_ON(I915_RESET_MODESET >= > > I915_RESET_ENGINE); > > + BUILD_BUG_ON(I915_RESET_WATCHDOG >= > > I915_RESET_ENGINE); > > if (test_and_set_bit(I915_RESET_ENGINE + > > engine->id, > > &dev_priv- > > >gpu_error.flags)) > > continue; > > @@ -4162,12 +4165,15 @@ static void gen8_gt_irq_postinstall(struct > > drm_i915_private *dev_priv) > > uint32_t gt_interrupts[] = { > > GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT | > > GT_CONTEXT_SWITCH_INTERRUPT << > > GEN8_RCS_IRQ_SHIFT | > > + GT_GEN8_WATCHDOG_INTERRUPT << > > GEN8_RCS_IRQ_SHIFT | > > GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT > > | > > GT_CONTEXT_SWITCH_INTERRUPT << > > GEN8_BCS_IRQ_SHIFT, > > GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT | > > GT_CONTEXT_SWITCH_INTERRUPT << > > GEN8_VCS1_IRQ_SHIFT | > > + GT_GEN8_WATCHDOG_INTERRUPT << > > GEN8_VCS1_IRQ_SHIFT | > > GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT > > | > > - GT_CONTEXT_SWITCH_INTERRUPT << > > GEN8_VCS2_IRQ_SHIFT, > > + GT_CONTEXT_SWITCH_INTERRUPT << > > GEN8_VCS2_IRQ_SHIFT | > > + GT_GEN8_WATCHDOG_INTERRUPT << > > GEN8_VCS2_IRQ_SHIFT, > > 0, > > GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT | > > GT_CONTEXT_SWITCH_INTERRUPT << > > GEN8_VECS_IRQ_SHIFT > > @@ -4176,6 +4182,10 @@ static void gen8_gt_irq_postinstall(struct > > drm_i915_private *dev_priv) > > if (HAS_L3_DPF(dev_priv)) > > gt_interrupts[0] |= > > GT_RENDER_L3_PARITY_ERROR_INTERRUPT; > > > > + /* VECS watchdog is only available in skl+ */ > > + if (INTEL_GEN(dev_priv) >= 9) > > + gt_interrupts[3] |= GT_GEN8_WATCHDOG_INTERRUPT; > > Is the shift missing here? > No, the above addresses the interrupts for the VECS watchdog only and the correct shift is applied in element 3 of the array. Regards, Carlos _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx