On 2019.01.21 11:51:41 +0200, Jani Nikula wrote:
> Mixed C99 and kernel types use is getting ugly. Prefer kernel types.
>
> sed -i 's/\buint\(8\|16\|32\|64\)_t\b/u\1/g'
>
> Signed-off-by: Jani Nikula <jani.nikula@xxxxxxxxx>
> ---
Looks good to me.
Acked-by: Zhenyu Wang <zhenyuw@xxxxxxxxxxxxxxx>
Will queue this up. Thanks!
> drivers/gpu/drm/i915/gvt/cmd_parser.c | 14 +++++++-------
> drivers/gpu/drm/i915/gvt/handlers.c | 6 +++---
> drivers/gpu/drm/i915/gvt/kvmgt.c | 24 ++++++++++++------------
> drivers/gpu/drm/i915/gvt/mmio.c | 6 +++---
> drivers/gpu/drm/i915/gvt/sched_policy.c | 2 +-
> drivers/gpu/drm/i915/gvt/scheduler.h | 2 +-
> 6 files changed, 27 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c
> index 77ae634eb11c..bac014031c4b 100644
> --- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
> +++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
> @@ -399,10 +399,10 @@ struct cmd_info {
> #define R_VECS (1 << VECS)
> #define R_ALL (R_RCS | R_VCS | R_BCS | R_VECS)
> /* rings that support this cmd: BLT/RCS/VCS/VECS */
> - uint16_t rings;
> + u16 rings;
>
> /* devices that support this cmd: SNB/IVB/HSW/... */
> - uint16_t devices;
> + u16 devices;
>
> /* which DWords are address that need fix up.
> * bit 0 means a 32-bit non address operand in command
> @@ -412,13 +412,13 @@ struct cmd_info {
> * No matter the address length, each address only takes
> * one bit in the bitmap.
> */
> - uint16_t addr_bitmap;
> + u16 addr_bitmap;
>
> /* flag == F_LEN_CONST : command length
> * flag == F_LEN_VAR : length bias bits
> * Note: length is in DWord
> */
> - uint8_t len;
> + u8 len;
>
> parser_cmd_handler handler;
> };
> @@ -1644,7 +1644,7 @@ static int find_bb_size(struct parser_exec_state *s, unsigned long *bb_size)
> {
> unsigned long gma = 0;
> struct cmd_info *info;
> - uint32_t cmd_len = 0;
> + u32 cmd_len = 0;
> bool bb_end = false;
> struct intel_vgpu *vgpu = s->vgpu;
> u32 cmd;
> @@ -2683,7 +2683,7 @@ static int scan_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
> I915_GTT_PAGE_SIZE)))
> return -EINVAL;
>
> - ring_tail = wa_ctx->indirect_ctx.size + 3 * sizeof(uint32_t);
> + ring_tail = wa_ctx->indirect_ctx.size + 3 * sizeof(u32);
> ring_size = round_up(wa_ctx->indirect_ctx.size + CACHELINE_BYTES,
> PAGE_SIZE);
> gma_head = wa_ctx->indirect_ctx.guest_gma;
> @@ -2850,7 +2850,7 @@ static int shadow_indirect_ctx(struct intel_shadow_wa_ctx *wa_ctx)
>
> static int combine_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
> {
> - uint32_t per_ctx_start[CACHELINE_DWORDS] = {0};
> + u32 per_ctx_start[CACHELINE_DWORDS] = {0};
> unsigned char *bb_start_sva;
>
> if (!wa_ctx->per_ctx.valid)
> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> index e9f343b124b0..2837baa55128 100644
> --- a/drivers/gpu/drm/i915/gvt/handlers.c
> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> @@ -276,7 +276,7 @@ static int mul_force_wake_write(struct intel_vgpu *vgpu,
> unsigned int offset, void *p_data, unsigned int bytes)
> {
> u32 old, new;
> - uint32_t ack_reg_offset;
> + u32 ack_reg_offset;
>
> old = vgpu_vreg(vgpu, offset);
> new = CALC_MODE_MASK_REG(old, *(u32 *)p_data);
> @@ -833,7 +833,7 @@ static int dp_aux_ch_ctl_trans_done(struct intel_vgpu *vgpu, u32 value,
> }
>
> static void dp_aux_ch_ctl_link_training(struct intel_vgpu_dpcd_data *dpcd,
> - uint8_t t)
> + u8 t)
> {
> if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == DPCD_TRAINING_PATTERN_1) {
> /* training pattern 1 for CR */
> @@ -919,7 +919,7 @@ static int dp_aux_ch_ctl_mmio_write(struct intel_vgpu *vgpu,
>
> if (op == GVT_AUX_NATIVE_WRITE) {
> int t;
> - uint8_t buf[16];
> + u8 buf[16];
>
> if ((addr + len + 1) >= DPCD_SIZE) {
> /*
> diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c
> index dd3dfd00f4e6..413c6a13ec02 100644
> --- a/drivers/gpu/drm/i915/gvt/kvmgt.c
> +++ b/drivers/gpu/drm/i915/gvt/kvmgt.c
> @@ -703,7 +703,7 @@ static void intel_vgpu_release_work(struct work_struct *work)
> __intel_vgpu_release(vgpu);
> }
>
> -static uint64_t intel_vgpu_get_bar_addr(struct intel_vgpu *vgpu, int bar)
> +static u64 intel_vgpu_get_bar_addr(struct intel_vgpu *vgpu, int bar)
> {
> u32 start_lo, start_hi;
> u32 mem_type;
> @@ -730,10 +730,10 @@ static uint64_t intel_vgpu_get_bar_addr(struct intel_vgpu *vgpu, int bar)
> return ((u64)start_hi << 32) | start_lo;
> }
>
> -static int intel_vgpu_bar_rw(struct intel_vgpu *vgpu, int bar, uint64_t off,
> +static int intel_vgpu_bar_rw(struct intel_vgpu *vgpu, int bar, u64 off,
> void *buf, unsigned int count, bool is_write)
> {
> - uint64_t bar_start = intel_vgpu_get_bar_addr(vgpu, bar);
> + u64 bar_start = intel_vgpu_get_bar_addr(vgpu, bar);
> int ret;
>
> if (is_write)
> @@ -745,13 +745,13 @@ static int intel_vgpu_bar_rw(struct intel_vgpu *vgpu, int bar, uint64_t off,
> return ret;
> }
>
> -static inline bool intel_vgpu_in_aperture(struct intel_vgpu *vgpu, uint64_t off)
> +static inline bool intel_vgpu_in_aperture(struct intel_vgpu *vgpu, u64 off)
> {
> return off >= vgpu_aperture_offset(vgpu) &&
> off < vgpu_aperture_offset(vgpu) + vgpu_aperture_sz(vgpu);
> }
>
> -static int intel_vgpu_aperture_rw(struct intel_vgpu *vgpu, uint64_t off,
> +static int intel_vgpu_aperture_rw(struct intel_vgpu *vgpu, u64 off,
> void *buf, unsigned long count, bool is_write)
> {
> void *aperture_va;
> @@ -783,7 +783,7 @@ static ssize_t intel_vgpu_rw(struct mdev_device *mdev, char *buf,
> {
> struct intel_vgpu *vgpu = mdev_get_drvdata(mdev);
> unsigned int index = VFIO_PCI_OFFSET_TO_INDEX(*ppos);
> - uint64_t pos = *ppos & VFIO_PCI_OFFSET_MASK;
> + u64 pos = *ppos & VFIO_PCI_OFFSET_MASK;
> int ret = -EINVAL;
>
>
> @@ -1039,7 +1039,7 @@ static int intel_vgpu_get_irq_count(struct intel_vgpu *vgpu, int type)
>
> static int intel_vgpu_set_intx_mask(struct intel_vgpu *vgpu,
> unsigned int index, unsigned int start,
> - unsigned int count, uint32_t flags,
> + unsigned int count, u32 flags,
> void *data)
> {
> return 0;
> @@ -1047,21 +1047,21 @@ static int intel_vgpu_set_intx_mask(struct intel_vgpu *vgpu,
>
> static int intel_vgpu_set_intx_unmask(struct intel_vgpu *vgpu,
> unsigned int index, unsigned int start,
> - unsigned int count, uint32_t flags, void *data)
> + unsigned int count, u32 flags, void *data)
> {
> return 0;
> }
>
> static int intel_vgpu_set_intx_trigger(struct intel_vgpu *vgpu,
> unsigned int index, unsigned int start, unsigned int count,
> - uint32_t flags, void *data)
> + u32 flags, void *data)
> {
> return 0;
> }
>
> static int intel_vgpu_set_msi_trigger(struct intel_vgpu *vgpu,
> unsigned int index, unsigned int start, unsigned int count,
> - uint32_t flags, void *data)
> + u32 flags, void *data)
> {
> struct eventfd_ctx *trigger;
>
> @@ -1080,12 +1080,12 @@ static int intel_vgpu_set_msi_trigger(struct intel_vgpu *vgpu,
> return 0;
> }
>
> -static int intel_vgpu_set_irqs(struct intel_vgpu *vgpu, uint32_t flags,
> +static int intel_vgpu_set_irqs(struct intel_vgpu *vgpu, u32 flags,
> unsigned int index, unsigned int start, unsigned int count,
> void *data)
> {
> int (*func)(struct intel_vgpu *vgpu, unsigned int index,
> - unsigned int start, unsigned int count, uint32_t flags,
> + unsigned int start, unsigned int count, u32 flags,
> void *data) = NULL;
>
> switch (index) {
> diff --git a/drivers/gpu/drm/i915/gvt/mmio.c b/drivers/gpu/drm/i915/gvt/mmio.c
> index 43f65848ecd6..ed4df2f6d60b 100644
> --- a/drivers/gpu/drm/i915/gvt/mmio.c
> +++ b/drivers/gpu/drm/i915/gvt/mmio.c
> @@ -57,7 +57,7 @@ int intel_vgpu_gpa_to_mmio_offset(struct intel_vgpu *vgpu, u64 gpa)
> (reg >= gvt->device_info.gtt_start_offset \
> && reg < gvt->device_info.gtt_start_offset + gvt_ggtt_sz(gvt))
>
> -static void failsafe_emulate_mmio_rw(struct intel_vgpu *vgpu, uint64_t pa,
> +static void failsafe_emulate_mmio_rw(struct intel_vgpu *vgpu, u64 pa,
> void *p_data, unsigned int bytes, bool read)
> {
> struct intel_gvt *gvt = NULL;
> @@ -99,7 +99,7 @@ static void failsafe_emulate_mmio_rw(struct intel_vgpu *vgpu, uint64_t pa,
> * Returns:
> * Zero on success, negative error code if failed
> */
> -int intel_vgpu_emulate_mmio_read(struct intel_vgpu *vgpu, uint64_t pa,
> +int intel_vgpu_emulate_mmio_read(struct intel_vgpu *vgpu, u64 pa,
> void *p_data, unsigned int bytes)
> {
> struct intel_gvt *gvt = vgpu->gvt;
> @@ -171,7 +171,7 @@ int intel_vgpu_emulate_mmio_read(struct intel_vgpu *vgpu, uint64_t pa,
> * Returns:
> * Zero on success, negative error code if failed
> */
> -int intel_vgpu_emulate_mmio_write(struct intel_vgpu *vgpu, uint64_t pa,
> +int intel_vgpu_emulate_mmio_write(struct intel_vgpu *vgpu, u64 pa,
> void *p_data, unsigned int bytes)
> {
> struct intel_gvt *gvt = vgpu->gvt;
> diff --git a/drivers/gpu/drm/i915/gvt/sched_policy.c b/drivers/gpu/drm/i915/gvt/sched_policy.c
> index f04b3b965bfc..1c763a27a412 100644
> --- a/drivers/gpu/drm/i915/gvt/sched_policy.c
> +++ b/drivers/gpu/drm/i915/gvt/sched_policy.c
> @@ -94,7 +94,7 @@ static void gvt_balance_timeslice(struct gvt_sched_data *sched_data)
> {
> struct vgpu_sched_data *vgpu_data;
> struct list_head *pos;
> - static uint64_t stage_check;
> + static u64 stage_check;
> int stage = stage_check++ % GVT_TS_BALANCE_STAGE_NUM;
>
> /* The timeslice accumulation reset at stage 0, which is
> diff --git a/drivers/gpu/drm/i915/gvt/scheduler.h b/drivers/gpu/drm/i915/gvt/scheduler.h
> index 2065cba59aab..0635b2c4bed7 100644
> --- a/drivers/gpu/drm/i915/gvt/scheduler.h
> +++ b/drivers/gpu/drm/i915/gvt/scheduler.h
> @@ -61,7 +61,7 @@ struct shadow_indirect_ctx {
> unsigned long guest_gma;
> unsigned long shadow_gma;
> void *shadow_va;
> - uint32_t size;
> + u32 size;
> };
>
> #define PER_CTX_ADDR_MASK 0xfffff000
> --
> 2.20.1
>
> _______________________________________________
> intel-gvt-dev mailing list
> intel-gvt-dev@xxxxxxxxxxxxxxxxxxxxx
> https://lists.freedesktop.org/mailman/listinfo/intel-gvt-dev
--
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