On Fri, 2019-01-11 at 12:44 -0800, José Roberto de Souza wrote:
> The value of this registers will be used to test if PSR2 is doing
> selective update and if the number of blocks match with the expected.
>
> v2:
> - Using new macros
> - Changed the string output
>
> v3:
> - reading PSR2_SU_STATUS registers together(Dhinakaran)
> - printing SU blocks of frames with 0 updates(Dhinakaran)
>
> Cc: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@xxxxxxxxx>
> Signed-off-by: José Roberto de Souza <jose.souza@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 23 +++++++++++++++++++++++
> 1 file changed, 23 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index f8668cb05d64..5817ae0fb5f8 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2600,6 +2600,29 @@ static int i915_edp_psr_status(struct seq_file
> *m, void *data)
> seq_printf(m, "Last exit at: %lld\n", psr->last_exit);
> }
>
> + if (psr->psr2_enabled) {
> + u32 su_frames_val[3];
> + u8 frame;
'int' seems like a more appropriate choice here. With that changed,
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@xxxxxxxxx>
Also, patch 2/4 needs rebase.
-DK
> +
> + /*
> + * Reading all 3 registers before hand to minimize
> crossing a
> + * frame boundary between register reads
> + */
> + for (frame = 0; frame < PSR2_SU_STATUS_FRAMES; frame +=
> 3)
> + su_frames_val[frame / 3] =
> I915_READ(PSR2_SU_STATUS(frame));
> +
> + seq_puts(m, "Frame:\tPSR2 SU blocks:\n");
> +
> + for (frame = 0; frame < PSR2_SU_STATUS_FRAMES; frame++)
> {
> + u32 su_blocks;
> +
> + su_blocks = su_frames_val[frame / 3] &
> + PSR2_SU_STATUS_MASK(frame);
> + su_blocks = su_blocks >>
> PSR2_SU_STATUS_SHIFT(frame);
> + seq_printf(m, "%d\t%d\n", frame, su_blocks);
> + }
> + }
> +
> unlock:
> mutex_unlock(&psr->lock);
> intel_runtime_pm_put(dev_priv);
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