>-----Original Message-----
>From: Roper, Matthew D
>Sent: Saturday, January 12, 2019 6:12 AM
>To: Ville Syrjala <ville.syrjala@xxxxxxxxxxxxxxx>
>Cc: intel-gfx@xxxxxxxxxxxxxxxxxxxxx; Shankar, Uma <uma.shankar@xxxxxxxxx>
>Subject: Re: [PATCH 04/13] drm/i915: Constify the state arguments to the color
>management stuff
>
>On Fri, Jan 11, 2019 at 07:08:14PM +0200, Ville Syrjala wrote:
>> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>>
>> Pass the crtc state etc. as const to the color management commit
>> functions. And while at it polish some of the local variables.
>>
>> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
>Reviewed-by: Matt Roper <matthew.d.roper@xxxxxxxxx>
Looks ok to me.
Reviewed-by: Uma Shankar <uma.shankar@xxxxxxxxx>
>> ---
>> drivers/gpu/drm/i915/i915_drv.h | 4 +-
>> drivers/gpu/drm/i915/intel_color.c | 128 ++++++++++++++++-------------
>> drivers/gpu/drm/i915/intel_drv.h | 4 +-
>> 3 files changed, 73 insertions(+), 63 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h
>> b/drivers/gpu/drm/i915/i915_drv.h index 5df26ccda8a4..7182a580002c
>> 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -320,8 +320,8 @@ struct drm_i915_display_funcs {
>> /* display clock increase/decrease */
>> /* pll clock increase/decrease */
>>
>> - void (*load_csc_matrix)(struct intel_crtc_state *crtc_state);
>> - void (*load_luts)(struct intel_crtc_state *crtc_state);
>> + void (*load_csc_matrix)(const struct intel_crtc_state *crtc_state);
>> + void (*load_luts)(const struct intel_crtc_state *crtc_state);
>> };
>>
>> #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
>> diff --git a/drivers/gpu/drm/i915/intel_color.c
>> b/drivers/gpu/drm/i915/intel_color.c
>> index b10e66ce3970..0dfd104b89d7 100644
>> --- a/drivers/gpu/drm/i915/intel_color.c
>> +++ b/drivers/gpu/drm/i915/intel_color.c
>> @@ -74,12 +74,12 @@
>> #define ILK_CSC_COEFF_1_0 \
>> ((7 << 12) | ILK_CSC_COEFF_FP(CTM_COEFF_1_0, 8))
>>
>> -static bool lut_is_legacy(struct drm_property_blob *lut)
>> +static bool lut_is_legacy(const struct drm_property_blob *lut)
>> {
>> return drm_color_lut_size(lut) == LEGACY_LUT_LENGTH; }
>>
>> -static bool crtc_state_is_legacy_gamma(struct intel_crtc_state
>> *crtc_state)
>> +static bool crtc_state_is_legacy_gamma(const struct intel_crtc_state
>> +*crtc_state)
>> {
>> return !crtc_state->base.degamma_lut &&
>> !crtc_state->base.ctm &&
>> @@ -115,8 +115,8 @@ static u64 *ctm_mult_by_limited(u64 *result, const
>> u64 *input)
>>
>> static void ilk_load_ycbcr_conversion_matrix(struct intel_crtc *crtc)
>> {
>> - int pipe = crtc->pipe;
>> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> + enum pipe pipe = crtc->pipe;
>>
>> I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
>> I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); @@ -137,13 +137,14 @@
>> static void ilk_load_ycbcr_conversion_matrix(struct intel_crtc *crtc)
>> I915_WRITE(PIPE_CSC_MODE(pipe), 0);
>> }
>>
>> -static void ilk_load_csc_matrix(struct intel_crtc_state *crtc_state)
>> +static void ilk_load_csc_matrix(const struct intel_crtc_state
>> +*crtc_state)
>> {
>> struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> - int i, pipe = crtc->pipe;
>> - uint16_t coeffs[9] = { 0, };
>> bool limited_color_range = false;
>> + enum pipe pipe = crtc->pipe;
>> + u16 coeffs[9] = {};
>> + int i;
>>
>> /*
>> * FIXME if there's a gamma LUT after the CSC, we should @@ -256,15
>> +257,15 @@ static void ilk_load_csc_matrix(struct intel_crtc_state
>> *crtc_state)
>> /*
>> * Set up the pipe CSC unit on CherryView.
>> */
>> -static void cherryview_load_csc_matrix(struct intel_crtc_state
>> *crtc_state)
>> +static void cherryview_load_csc_matrix(const struct intel_crtc_state
>> +*crtc_state)
>> {
>> - struct drm_device *dev = crtc_state->base.crtc->dev;
>> - struct drm_i915_private *dev_priv = to_i915(dev);
>> - int pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
>> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> + enum pipe pipe = crtc->pipe;
>> uint32_t mode;
>>
>> if (crtc_state->base.ctm) {
>> - struct drm_color_ctm *ctm = crtc_state->base.ctm->data;
>> + const struct drm_color_ctm *ctm = crtc_state->base.ctm->data;
>> uint16_t coeffs[9] = { 0, };
>> int i;
>>
>> @@ -303,18 +304,17 @@ static void cherryview_load_csc_matrix(struct
>intel_crtc_state *crtc_state)
>> I915_WRITE(CGM_PIPE_MODE(pipe), mode); }
>>
>> -void intel_color_set_csc(struct intel_crtc_state *crtc_state)
>> +void intel_color_set_csc(const struct intel_crtc_state *crtc_state)
>> {
>> - struct drm_device *dev = crtc_state->base.crtc->dev;
>> - struct drm_i915_private *dev_priv = to_i915(dev);
>> + struct drm_i915_private *dev_priv =
>> +to_i915(crtc_state->base.crtc->dev);
>>
>> if (dev_priv->display.load_csc_matrix)
>> dev_priv->display.load_csc_matrix(crtc_state);
>> }
>>
>> /* Loads the legacy palette/gamma unit for the CRTC. */ -static void
>> i9xx_load_luts_internal(struct intel_crtc_state *crtc_state,
>> - struct drm_property_blob *blob)
>> +static void i9xx_load_luts_internal(const struct intel_crtc_state *crtc_state,
>> + const struct drm_property_blob *blob)
>> {
>> struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); @@
>> -329,7 +329,8 @@ static void i9xx_load_luts_internal(struct intel_crtc_state
>*crtc_state,
>> }
>>
>> if (blob) {
>> - struct drm_color_lut *lut = blob->data;
>> + const struct drm_color_lut *lut = blob->data;
>> +
>> for (i = 0; i < 256; i++) {
>> uint32_t word =
>> (drm_color_lut_extract(lut[i].red, 8) << 16) |
>@@ -353,13 +354,13
>> @@ static void i9xx_load_luts_internal(struct intel_crtc_state *crtc_state,
>> }
>> }
>>
>> -static void i9xx_load_luts(struct intel_crtc_state *crtc_state)
>> +static void i9xx_load_luts(const struct intel_crtc_state *crtc_state)
>> {
>> i9xx_load_luts_internal(crtc_state, crtc_state->base.gamma_lut); }
>>
>> /* Loads the legacy palette/gamma unit for the CRTC on Haswell. */
>> -static void haswell_load_luts(struct intel_crtc_state *crtc_state)
>> +static void haswell_load_luts(const struct intel_crtc_state
>> +*crtc_state)
>> {
>> struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); @@
>> -383,17 +384,19 @@ static void haswell_load_luts(struct intel_crtc_state
>*crtc_state)
>> hsw_enable_ips(crtc_state);
>> }
>>
>> -static void bdw_load_degamma_lut(struct intel_crtc_state *crtc_state)
>> +static void bdw_load_degamma_lut(const struct intel_crtc_state
>> +*crtc_state)
>> {
>> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
>> - enum pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
>> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> + const struct drm_property_blob *degamma_lut =
>> +crtc_state->base.degamma_lut;
>> uint32_t i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
>> + enum pipe pipe = crtc->pipe;
>>
>> I915_WRITE(PREC_PAL_INDEX(pipe),
>> PAL_PREC_SPLIT_MODE | PAL_PREC_AUTO_INCREMENT);
>>
>> - if (crtc_state->base.degamma_lut) {
>> - struct drm_color_lut *lut = crtc_state->base.degamma_lut-
>>data;
>> + if (degamma_lut) {
>> + const struct drm_color_lut *lut = degamma_lut->data;
>>
>> for (i = 0; i < lut_size; i++) {
>> uint32_t word =
>> @@ -413,11 +416,13 @@ static void bdw_load_degamma_lut(struct
>intel_crtc_state *crtc_state)
>> }
>> }
>>
>> -static void bdw_load_gamma_lut(struct intel_crtc_state *crtc_state,
>> u32 offset)
>> +static void bdw_load_gamma_lut(const struct intel_crtc_state
>> +*crtc_state, u32 offset)
>> {
>> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
>> - enum pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
>> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> + const struct drm_property_blob *gamma_lut =
>> +crtc_state->base.gamma_lut;
>> uint32_t i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
>> + enum pipe pipe = crtc->pipe;
>>
>> WARN_ON(offset & ~PAL_PREC_INDEX_VALUE_MASK);
>>
>> @@ -426,8 +431,8 @@ static void bdw_load_gamma_lut(struct
>intel_crtc_state *crtc_state, u32 offset)
>> PAL_PREC_AUTO_INCREMENT |
>> offset);
>>
>> - if (crtc_state->base.gamma_lut) {
>> - struct drm_color_lut *lut = crtc_state->base.gamma_lut->data;
>> + if (gamma_lut) {
>> + const struct drm_color_lut *lut = gamma_lut->data;
>>
>> for (i = 0; i < lut_size; i++) {
>> uint32_t word =
>> @@ -461,10 +466,11 @@ static void bdw_load_gamma_lut(struct
>> intel_crtc_state *crtc_state, u32 offset) }
>>
>> /* Loads the palette/gamma unit for the CRTC on Broadwell+. */
>> -static void broadwell_load_luts(struct intel_crtc_state *crtc_state)
>> +static void broadwell_load_luts(const struct intel_crtc_state
>> +*crtc_state)
>> {
>> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
>> - enum pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
>> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> + enum pipe pipe = crtc->pipe;
>>
>> if (crtc_state_is_legacy_gamma(crtc_state)) {
>> haswell_load_luts(crtc_state);
>> @@ -484,10 +490,11 @@ static void broadwell_load_luts(struct
>intel_crtc_state *crtc_state)
>> I915_WRITE(PREC_PAL_INDEX(pipe), 0); }
>>
>> -static void glk_load_degamma_lut(struct intel_crtc_state *crtc_state)
>> +static void glk_load_degamma_lut(const struct intel_crtc_state
>> +*crtc_state)
>> {
>> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
>> - enum pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
>> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> + enum pipe pipe = crtc->pipe;
>> const uint32_t lut_size = 33;
>> uint32_t i;
>>
>> @@ -514,11 +521,11 @@ static void glk_load_degamma_lut(struct
>intel_crtc_state *crtc_state)
>> I915_WRITE(PRE_CSC_GAMC_DATA(pipe), (1 << 16)); }
>>
>> -static void glk_load_luts(struct intel_crtc_state *crtc_state)
>> +static void glk_load_luts(const struct intel_crtc_state *crtc_state)
>> {
>> - struct drm_device *dev = crtc_state->base.crtc->dev;
>> - struct drm_i915_private *dev_priv = to_i915(dev);
>> - enum pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
>> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> + enum pipe pipe = crtc->pipe;
>>
>> glk_load_degamma_lut(crtc_state);
>>
>> @@ -532,28 +539,29 @@ static void glk_load_luts(struct intel_crtc_state
>*crtc_state)
>> I915_WRITE(GAMMA_MODE(pipe), crtc_state->gamma_mode); }
>>
>> -/* Loads the palette/gamma unit for the CRTC on CherryView. */
>> -static void cherryview_load_luts(struct intel_crtc_state *crtc_state)
>> +static void cherryview_load_luts(const struct intel_crtc_state
>> +*crtc_state)
>> {
>> - struct drm_crtc *crtc = crtc_state->base.crtc;
>> - struct drm_i915_private *dev_priv = to_i915(crtc->dev);
>> - enum pipe pipe = to_intel_crtc(crtc)->pipe;
>> - struct drm_color_lut *lut;
>> - uint32_t i, lut_size;
>> - uint32_t word0, word1;
>> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> + const struct drm_property_blob *gamma_lut = crtc_state-
>>base.gamma_lut;
>> + const struct drm_property_blob *degamma_lut = crtc_state-
>>base.degamma_lut;
>> + enum pipe pipe = crtc->pipe;
>>
>> if (crtc_state_is_legacy_gamma(crtc_state)) {
>> /* Turn off degamma/gamma on CGM block. */
>> I915_WRITE(CGM_PIPE_MODE(pipe),
>> (crtc_state->base.ctm ? CGM_PIPE_MODE_CSC : 0));
>> - i9xx_load_luts_internal(crtc_state, crtc_state-
>>base.gamma_lut);
>> + i9xx_load_luts_internal(crtc_state, gamma_lut);
>> return;
>> }
>>
>> - if (crtc_state->base.degamma_lut) {
>> - lut = crtc_state->base.degamma_lut->data;
>> - lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
>> + if (degamma_lut) {
>> + const struct drm_color_lut *lut = degamma_lut->data;
>> + int i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
>> +
>> for (i = 0; i < lut_size; i++) {
>> + u32 word0, word1;
>> +
>> /* Write LUT in U0.14 format. */
>> word0 =
>> (drm_color_lut_extract(lut[i].green, 14) << 16) | @@ -
>565,10
>> +573,13 @@ static void cherryview_load_luts(struct intel_crtc_state
>*crtc_state)
>> }
>> }
>>
>> - if (crtc_state->base.gamma_lut) {
>> - lut = crtc_state->base.gamma_lut->data;
>> - lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
>> + if (gamma_lut) {
>> + const struct drm_color_lut *lut = gamma_lut->data;
>> + int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
>> +
>> for (i = 0; i < lut_size; i++) {
>> + u32 word0, word1;
>> +
>> /* Write LUT in U0.10 format. */
>> word0 =
>> (drm_color_lut_extract(lut[i].green, 10) << 16) | @@ -
>582,8 +593,8
>> @@ static void cherryview_load_luts(struct intel_crtc_state
>> *crtc_state)
>>
>> I915_WRITE(CGM_PIPE_MODE(pipe),
>> (crtc_state->base.ctm ? CGM_PIPE_MODE_CSC : 0) |
>> - (crtc_state->base.degamma_lut ?
>CGM_PIPE_MODE_DEGAMMA : 0) |
>> - (crtc_state->base.gamma_lut ? CGM_PIPE_MODE_GAMMA :
>0));
>> + (degamma_lut ? CGM_PIPE_MODE_DEGAMMA : 0) |
>> + (gamma_lut ? CGM_PIPE_MODE_GAMMA : 0));
>>
>> /*
>> * Also program a linear LUT in the legacy block (behind the @@
>> -592,10 +603,9 @@ static void cherryview_load_luts(struct intel_crtc_state
>*crtc_state)
>> i9xx_load_luts_internal(crtc_state, NULL); }
>>
>> -void intel_color_load_luts(struct intel_crtc_state *crtc_state)
>> +void intel_color_load_luts(const struct intel_crtc_state *crtc_state)
>> {
>> - struct drm_device *dev = crtc_state->base.crtc->dev;
>> - struct drm_i915_private *dev_priv = to_i915(dev);
>> + struct drm_i915_private *dev_priv =
>> +to_i915(crtc_state->base.crtc->dev);
>>
>> dev_priv->display.load_luts(crtc_state);
>> }
>> diff --git a/drivers/gpu/drm/i915/intel_drv.h
>> b/drivers/gpu/drm/i915/intel_drv.h
>> index 88ac42b2d7ed..96743f50b13a 100644
>> --- a/drivers/gpu/drm/i915/intel_drv.h
>> +++ b/drivers/gpu/drm/i915/intel_drv.h
>> @@ -2338,8 +2338,8 @@ int intel_plane_atomic_check_with_state(const
>> struct intel_crtc_state *old_crtc_
>> /* intel_color.c */
>> void intel_color_init(struct intel_crtc *crtc); int
>> intel_color_check(struct intel_crtc_state *crtc_state); -void
>> intel_color_set_csc(struct intel_crtc_state *crtc_state); -void
>> intel_color_load_luts(struct intel_crtc_state *crtc_state);
>> +void intel_color_set_csc(const struct intel_crtc_state *crtc_state);
>> +void intel_color_load_luts(const struct intel_crtc_state
>> +*crtc_state);
>>
>> /* intel_lspcon.c */
>> bool lspcon_init(struct intel_digital_port *intel_dig_port);
>> --
>> 2.19.2
>>
>
>--
>Matt Roper
>Graphics Software Engineer
>IoTG Platform Enabling & Development
>Intel Corporation
>(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
