On Tue, Jan 08, 2019 at 12:32:05PM -0800, Kenneth Graunke wrote: > On Tuesday, January 8, 2019 7:53:05 AM PST Joonas Lahtinen wrote: > > + Ken/Jason for Mesa > > Quoting Matt Roper (2019-01-07 21:19:31) > > > On Mon, Jan 07, 2019 at 01:23:50PM +0100, Michał Winiarski wrote: > > > > On Mon, Jan 07, 2019 at 01:01:16PM +0200, Joonas Lahtinen wrote: > > > > > Quoting José Roberto de Souza (2019-01-04 19:37:00) > > > > > > According to Workaround database ICL also needs > > > > > > WaEnablePreemptionGranularityControlByUMD, to allow userspace to do > > > > > > fine-granularity preemptions per-context. > > > > > > > > > > I must wonder where is the userspace component that needs this, and why > > > > > it hasn't been noticed earlier? > > > > > > > > > > Or is this one more of the cases when no userspace actually uses the > > > > > register? > > > > > > > > It's used: > > > > https://gitlab.freedesktop.org/mesa/mesa/blob/master/src/mesa/drivers/dri/i965/brw_state_upload.c#L64 > > > > > > > > -Michał > > > > > > Wasn't this just an artificial i915-only workaround that was added to > > > prevent breakage of pre-preemption UMD's? Initial gen9 driver releases > > > didn't support preemption, so when preemption support did get added to > > > i915, the kernel had to force object-level off by default at context > > > creation to avoid breaking old userspace that didn't build batch buffers > > > with all the necessary preemption workarounds. This CS_CHICKEN1 > > > register was then exposed to userspace so that newer, preemption-aware > > > userspace could opt back in if it properly supported preemption. It's not only that userspace didn't build proper batch buffers with the necessary workarounds, but that most of the workarounds required disabling preemption depending on the type of primitive being drawn. So userspace needed access to CS_CHICKEN1 to be able to enable/disable preemption for those. > > > For gen11, there shouldn't be any "old" userspace around that doesn't > > > support preemption, so shouldn't the kernel just leave object-level > > > preemption enabled by default (meaning there's no need to expose this > > > register to userspace to allow it to explicitly opt-in)? > > > > Makes sense to me. We should have known by know if somebody expects to > > control the register, because they would be failing to do so. > > > > Mesa could also drop the register load for Gen11+ > > > > Regards, Joonas > > + Rafael, as he's done all the preemption work in Mesa. > > That seems reasonable to me. It looks like i965 always enables > mid-object preemption (sets CS_CHICKEN1 bit 0) on Gen10+, and never > disables it. You can probably safely turn it on by default, and we > can stop writing the register altogether. Yeah, I noticed this after re-reading some other thread, right after we got the preemption patches merged. On gen11, we have some workarounds but they don't require us to disable preemption through CS_CHICKEN1, so it should be safe for the kernel to not whitelist or disable it. Thanks, Rafael _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
