On Fri, Jan 11, 2019 at 07:08:13PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> We shouldn't be computing gamma mode during the commit phase.
> Move it to the check phase.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Looks like this also drops the posting reads, but I don't see anything
in the bspec that indicates those were necessary in the first place.
> ---
> drivers/gpu/drm/i915/intel_color.c | 44 +++++++++++++++++-------------
> 1 file changed, 25 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
> index 37fd9ddf762e..b10e66ce3970 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -375,8 +375,7 @@ static void haswell_load_luts(struct intel_crtc_state *crtc_state)
> reenable_ips = true;
> }
>
> - crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
> - I915_WRITE(GAMMA_MODE(crtc->pipe), GAMMA_MODE_MODE_8BIT);
> + I915_WRITE(GAMMA_MODE(crtc->pipe), crtc_state->gamma_mode);
>
> i9xx_load_luts(crtc_state);
>
> @@ -476,9 +475,7 @@ static void broadwell_load_luts(struct intel_crtc_state *crtc_state)
> bdw_load_gamma_lut(crtc_state,
> INTEL_INFO(dev_priv)->color.degamma_lut_size);
>
> - crtc_state->gamma_mode = GAMMA_MODE_MODE_SPLIT;
> - I915_WRITE(GAMMA_MODE(pipe), GAMMA_MODE_MODE_SPLIT);
> - POSTING_READ(GAMMA_MODE(pipe));
> + I915_WRITE(GAMMA_MODE(pipe), crtc_state->gamma_mode);
>
> /*
> * Reset the index, otherwise it prevents the legacy palette to be
> @@ -532,9 +529,7 @@ static void glk_load_luts(struct intel_crtc_state *crtc_state)
>
> bdw_load_gamma_lut(crtc_state, 0);
>
> - crtc_state->gamma_mode = GAMMA_MODE_MODE_10BIT;
> - I915_WRITE(GAMMA_MODE(pipe), GAMMA_MODE_MODE_10BIT);
> - POSTING_READ(GAMMA_MODE(pipe));
> + I915_WRITE(GAMMA_MODE(pipe), crtc_state->gamma_mode);
> }
>
> /* Loads the palette/gamma unit for the CRTC on CherryView. */
> @@ -608,29 +603,40 @@ void intel_color_load_luts(struct intel_crtc_state *crtc_state)
> int intel_color_check(struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> + const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
> + const struct drm_property_blob *degamma_lut = crtc_state->base.degamma_lut;
> size_t gamma_length, degamma_length;
>
> degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size;
> gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size;
>
> /*
> - * We allow both degamma & gamma luts at the right size or
> - * NULL.
> + * We also allow no degamma lut/ctm and a gamma lut at the legacy
> + * size (256 entries).
> */
Minor nit: now that the order of tests is swapped, you probably want
to move the "also" from this comment down to the one below.
Otherwise,
Reviewed-by: Matt Roper <matthew.d.roper@xxxxxxxxx>
> - if ((!crtc_state->base.degamma_lut ||
> - drm_color_lut_size(crtc_state->base.degamma_lut) == degamma_length) &&
> - (!crtc_state->base.gamma_lut ||
> - drm_color_lut_size(crtc_state->base.gamma_lut) == gamma_length))
> + if (crtc_state_is_legacy_gamma(crtc_state)) {
> + crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
> return 0;
> + }
>
> /*
> - * We also allow no degamma lut/ctm and a gamma lut at the legacy
> - * size (256 entries).
> + * We allow both degamma & gamma luts at the right size or
> + * NULL.
> */
> - if (crtc_state_is_legacy_gamma(crtc_state))
> - return 0;
> + if (degamma_lut && drm_color_lut_size(degamma_lut) != degamma_length)
> + return -EINVAL;
> +
> + if (gamma_lut && drm_color_lut_size(gamma_lut) != gamma_length)
> + return -EINVAL;
> +
> + if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> + crtc_state->gamma_mode = GAMMA_MODE_MODE_10BIT;
> + else if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
> + crtc_state->gamma_mode = GAMMA_MODE_MODE_SPLIT;
> + else
> + crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
>
> - return -EINVAL;
> + return 0;
> }
>
> void intel_color_init(struct intel_crtc *crtc)
> --
> 2.19.2
>
--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
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