== Series Details == Series: Enable/disable gamma/csc dynamically and fix C8 URL : https://patchwork.freedesktop.org/series/55081/ State : warning == Summary == $ dim checkpatch origin/drm-tip 066d50880adb drm/i915: Clean up intel_plane_atomic_check_with_state() 43cec2bfb86d drm/i915: Split the gamma/csc enable bits from the plane_ctl() function c0564fda1b3b drm/i915: Precompute gamma_mode 9c79ce51c6e6 drm/i915: Constify the state arguments to the color management stuff e4f2442c4803 drm/i915: Pull GAMMA_MODE write out from haswell_load_luts() eb35618583b0 drm/i915: Split color mgmt based on single vs. double buffered registers 544c73d70496 drm/i915: Move LUT programming to happen after vblank waits d957bacac7cd drm/i915: Populate gamma_mode for all platforms -:34: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV) #34: FILE: drivers/gpu/drm/i915/i915_reg.h:5588: +#define PIPECONF_GAMMA_MODE(x) ((x)<<24) /* pass in GAMMA_MODE_MODE_* */ ^ total: 0 errors, 0 warnings, 1 checks, 146 lines checked 7fb08d2ae464 drm/i915: Track pipe gamma enable/disable in crtc state 88de7f4faa5a drm/i915: Track pipe csc enable in crtc state da7ea155c150 drm/i915: Turn off pipe gamma when it's not needed. 00cf0ace1712 drm/i915: Turn off pipe CSC when it's not needed cb493c538af7 drm/i915: Disable pipe gamma when C8 pixel format is used _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
