On 07/01/2019 11:28, Chris Wilson wrote:
If we do not know the underlying swizzle on the HW, we do not know the
full tiling pattern and cannot predict the expected results. This is
often because the swizzle varies between pages and is not as constant as
we naively expected.
Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
---
tests/i915/gem_tiled_pread_basic.c | 23 ++++++++++++++++++++++-
tests/i915/gem_tiled_pread_pwrite.c | 23 ++++++++++++++++++++++-
2 files changed, 44 insertions(+), 2 deletions(-)
diff --git a/tests/i915/gem_tiled_pread_basic.c b/tests/i915/gem_tiled_pread_basic.c
index 425bb07e7..48b1b37e2 100644
--- a/tests/i915/gem_tiled_pread_basic.c
+++ b/tests/i915/gem_tiled_pread_basic.c
@@ -61,6 +61,27 @@ static int tile_width;
static int tile_height;
static int tile_size;
+static void
+get_tiling(int fd, uint32_t handle, uint32_t *tiling, uint32_t *swizzle)
+{
+ struct drm_i915_gem_get_tiling2 {
+ uint32_t handle;
+ uint32_t tiling_mode;
+ uint32_t swizzle_mode;
+ uint32_t phys_swizzle_mode;
+ } arg;
+#define DRM_IOCTL_I915_GEM_GET_TILING2 DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling2)
+
+ memset(&arg, 0, sizeof(arg));
+ arg.handle = handle;
+
+ do_ioctl(fd, DRM_IOCTL_I915_GEM_GET_TILING2, &arg);
+ igt_require(arg.phys_swizzle_mode == arg.swizzle_mode);
+
+ *tiling = arg.tiling_mode;
+ *swizzle = arg.swizzle_mode;
+}
Awooga! Third copy consolidates. ;)
Common gem_get_tiling and igt_require in the callers? Hm wait,
gem_get_tiling looks identical. What's the catch?
Regards,
Tvrtko
+
static uint32_t
create_bo(int fd)
{
@@ -125,7 +146,7 @@ igt_simple_main
fd = drm_open_driver(DRIVER_INTEL);
handle = create_bo(fd);
- igt_require(gem_get_tiling(fd, handle, &tiling, &swizzle));
+ get_tiling(fd, handle, &tiling, &swizzle);
devid = intel_get_drm_devid(fd);
diff --git a/tests/i915/gem_tiled_pread_pwrite.c b/tests/i915/gem_tiled_pread_pwrite.c
index 313daa388..59afae896 100644
--- a/tests/i915/gem_tiled_pread_pwrite.c
+++ b/tests/i915/gem_tiled_pread_pwrite.c
@@ -69,6 +69,27 @@ static uint32_t current_tiling_mode;
#define PAGE_SIZE 4096
+static void
+get_tiling(int fd, uint32_t handle, uint32_t *tiling, uint32_t *swizzle)
+{
+ struct drm_i915_gem_get_tiling2 {
+ uint32_t handle;
+ uint32_t tiling_mode;
+ uint32_t swizzle_mode;
+ uint32_t phys_swizzle_mode;
+ } arg;
+#define DRM_IOCTL_I915_GEM_GET_TILING2 DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling2)
+
+ memset(&arg, 0, sizeof(arg));
+ arg.handle = handle;
+
+ do_ioctl(fd, DRM_IOCTL_I915_GEM_GET_TILING2, &arg);
+ igt_require(arg.phys_swizzle_mode == arg.swizzle_mode);
+
+ *tiling = arg.tiling_mode;
+ *swizzle = arg.swizzle_mode;
+}
+
static uint32_t
create_bo_and_fill(int fd)
{
@@ -122,7 +143,7 @@ igt_simple_main
current_tiling_mode = I915_TILING_X;
handle = create_bo_and_fill(fd);
- gem_get_tiling(fd, handle, &tiling, &swizzle);
+ get_tiling(fd, handle, &tiling, &swizzle);
gem_read(fd, handle, 0, linear, sizeof(linear));
_______________________________________________
Intel-gfx mailing list
Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
