Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> writes:
> The additional flushes for gen7 appear to have been a red herring as the
> more efficacious workaround seems to be commit 476af9c26063 ("drm/i915/gen6:
> Flush RING_IMR changes before changing the global GT IMR"). Trusting the
> updated results means we can remove the special casing for gen7_xcs and
> reduce it to the gen6_xcs_emit_breadcrumb.
>
> References: 476af9c26063 ("drm/i915/gen6: Flush RING_IMR changes before changing the global GT IMR")
> Fixes: 1212bd821de8 ("drm/i915/ringbuffer: Move irq seqno barrier to the GPU for gen7")
> Testcase: igt/gem_sync
This would be nice simplification but gem_sync failed on hsw. I tried to
look at the details but the web page on shards says it has not run yet (?)
-Mika
> Testcase: igt/gem_exec_whisper
> Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_ringbuffer.c | 54 ++++---------------------
> 1 file changed, 8 insertions(+), 46 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 3d5d6b908148..2ac0c3a0d473 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -433,8 +433,8 @@ static const int gen7_rcs_emit_breadcrumb_sz = 6;
>
> static void gen6_xcs_emit_breadcrumb(struct i915_request *rq, u32 *cs)
> {
> - *cs++ = MI_FLUSH_DW | MI_FLUSH_DW_OP_STOREDW;
> - *cs++ = intel_hws_seqno_address(rq->engine) | MI_FLUSH_DW_USE_GTT;
> + *cs++ = MI_FLUSH_DW | MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_STORE_INDEX;
> + *cs++ = I915_GEM_HWS_INDEX_ADDR | MI_FLUSH_DW_USE_GTT;
> *cs++ = rq->global_seqno;
> *cs++ = MI_USER_INTERRUPT;
>
> @@ -443,34 +443,6 @@ static void gen6_xcs_emit_breadcrumb(struct i915_request *rq, u32 *cs)
> }
> static const int gen6_xcs_emit_breadcrumb_sz = 4;
>
> -#define GEN7_XCS_WA 32
> -static void gen7_xcs_emit_breadcrumb(struct i915_request *rq, u32 *cs)
> -{
> - int i;
> -
> - *cs++ = MI_FLUSH_DW | MI_FLUSH_DW_OP_STOREDW;
> - *cs++ = intel_hws_seqno_address(rq->engine) | MI_FLUSH_DW_USE_GTT;
> - *cs++ = rq->global_seqno;
> -
> - for (i = 0; i < GEN7_XCS_WA; i++) {
> - *cs++ = MI_STORE_DWORD_INDEX;
> - *cs++ = I915_GEM_HWS_INDEX_ADDR;
> - *cs++ = rq->global_seqno;
> - }
> -
> - *cs++ = MI_FLUSH_DW;
> - *cs++ = 0;
> - *cs++ = 0;
> -
> - *cs++ = MI_USER_INTERRUPT;
> - *cs++ = MI_NOOP;
> -
> - rq->tail = intel_ring_offset(rq, cs);
> - assert_ring_tail_valid(rq->ring, rq->tail);
> -}
> -static const int gen7_xcs_emit_breadcrumb_sz = 8 + GEN7_XCS_WA * 3;
> -#undef GEN7_XCS_WA
> -
> static void set_hwstam(struct intel_engine_cs *engine, u32 mask)
> {
> /*
> @@ -2267,13 +2239,8 @@ int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine)
> engine->emit_flush = gen6_bsd_ring_flush;
> engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;
>
> - if (IS_GEN(dev_priv, 6)) {
> - engine->emit_breadcrumb = gen6_xcs_emit_breadcrumb;
> - engine->emit_breadcrumb_sz = gen6_xcs_emit_breadcrumb_sz;
> - } else {
> - engine->emit_breadcrumb = gen7_xcs_emit_breadcrumb;
> - engine->emit_breadcrumb_sz = gen7_xcs_emit_breadcrumb_sz;
> - }
> + engine->emit_breadcrumb = gen6_xcs_emit_breadcrumb;
> + engine->emit_breadcrumb_sz = gen6_xcs_emit_breadcrumb_sz;
> } else {
> engine->emit_flush = bsd_ring_flush;
> if (IS_GEN(dev_priv, 5))
> @@ -2296,13 +2263,8 @@ int intel_init_blt_ring_buffer(struct intel_engine_cs *engine)
> engine->emit_flush = gen6_ring_flush;
> engine->irq_enable_mask = GT_BLT_USER_INTERRUPT;
>
> - if (IS_GEN(dev_priv, 6)) {
> - engine->emit_breadcrumb = gen6_xcs_emit_breadcrumb;
> - engine->emit_breadcrumb_sz = gen6_xcs_emit_breadcrumb_sz;
> - } else {
> - engine->emit_breadcrumb = gen7_xcs_emit_breadcrumb;
> - engine->emit_breadcrumb_sz = gen7_xcs_emit_breadcrumb_sz;
> - }
> + engine->emit_breadcrumb = gen6_xcs_emit_breadcrumb;
> + engine->emit_breadcrumb_sz = gen6_xcs_emit_breadcrumb_sz;
>
> return intel_init_ring_buffer(engine);
> }
> @@ -2320,8 +2282,8 @@ int intel_init_vebox_ring_buffer(struct intel_engine_cs *engine)
> engine->irq_enable = hsw_vebox_irq_enable;
> engine->irq_disable = hsw_vebox_irq_disable;
>
> - engine->emit_breadcrumb = gen7_xcs_emit_breadcrumb;
> - engine->emit_breadcrumb_sz = gen7_xcs_emit_breadcrumb_sz;
> + engine->emit_breadcrumb = gen6_xcs_emit_breadcrumb;
> + engine->emit_breadcrumb_sz = gen6_xcs_emit_breadcrumb_sz;
>
> return intel_init_ring_buffer(engine);
> }
> --
> 2.20.1
>
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