On Thu, 26 Jul 2012 11:16:14 +0200, Daniel Vetter <daniel.vetter at ffwll.ch> wrote: > The power docs say that when the gt leaves rc6, it is in the lowest > frequency and only about 25 usec later will switch to the frequency > selected in GEN6_RPNSWREQ. If the downclock limit expires in that > window and the down limit is set to the lowest possible frequency, the > hw will not send the down interrupt. Which leads to a too high gpu > clock and wasted power. > > Chris Wilson already worked on this with > > commit 7b9e0ae6da0a7eaf2680a1a788f08df123724f3b > Author: Chris Wilson <chris at chris-wilson.co.uk> > Date: Sat Apr 28 08:56:39 2012 +0100 > > drm/i915: Always update RPS interrupts thresholds along with > frequency > > but got the logic inverted: The current code set the down limit as > long as we haven't reached it. Instead of only once with reached the > lowest frequency. > > Note that we can't always set the downclock limit to 0, because > otherwise the hw will keep on bugging us with downclock request irqs > once the lowest level is reached. > > For similar reasons also always set the upclock limit, otherwise the > hw might poke us again with interrupts. > > v2: Chris Wilson noticed that the limit reg is also computed in > sanitize_pm. To avoid duplication, extract the code into a common > function. Aye, that's the patch I wish I wrote. Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk> Though since I was clearly confused in the first place... -Chris -- Chris Wilson, Intel Open Source Technology Centre
