Talha Nassar <talha.nassar@xxxxxxxxx> writes: > From: talha nassar <talha.nassar@xxxxxxxxx> > > HW team confirmed that this register is write-only. It could be that it is that bit only. We don't need to care about that now, Reviewed-by: Mika Kuoppala <mika.kuoppala@xxxxxxxxxxxxxxx> > > References: https://bugs.freedesktop.org/show_bug.cgi?id=107338 > Cc: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> > Cc: Mika Kuoppala <mika.kuoppala@xxxxxxxxxxxxxxx> > Signed-off-by: talha nassar <talha.nassar@xxxxxxxxx> > --- > tests/i915/gem_workarounds.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/tests/i915/gem_workarounds.c b/tests/i915/gem_workarounds.c > index 78478ad..b7d7d9c 100644 > --- a/tests/i915/gem_workarounds.c > +++ b/tests/i915/gem_workarounds.c > @@ -51,7 +51,8 @@ static struct write_only_list { > unsigned int gen; > uint32_t addr; > } wo_list[] = { > - { 10, 0xE5F0 } /* WaForceContextSaveRestoreNonCoherent:cnl */ > + { 10, 0xE5F0 }, /* WaForceContextSaveRestoreNonCoherent:cnl */ > + { 11, 0xE420 } /* WaEnableFloatBlendOptimization:icl */ > > /* > * FIXME: If you are contemplating adding stuff here > -- > 2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
