== Series Details == Series: series starting with [1/3] drm/i915: Prepare for larger CSB status FIFO size URL : https://patchwork.freedesktop.org/series/54213/ State : warning == Summary == $ dim checkpatch origin/drm-tip c158aa2a2dad drm/i915: Prepare for larger CSB status FIFO size -:133: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i' - possible side-effects? #133: FILE: drivers/gpu/drm/i915/intel_lrc.h:40: +#define _RING_CSB_OFFSET(i) ((i) < 6 ? \ + (0x370 + (i) * 8) : \ + (0x3c0 + ((i) - 6) * 8)) total: 0 errors, 0 warnings, 1 checks, 132 lines checked 8ab507eb3069 drm/i915/icl: Switch to using 12 deep CSB status FIFO c801d4fe14d8 drm/i915/icl: Introduce gen11 flush/invalidate -:25: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV) #25: FILE: drivers/gpu/drm/i915/intel_gpu_commands.h:198: +#define PIPE_CONTROL_COMMAND_CACHE_INVALIDATE (1<<29) /* gen11+ */ ^ -:26: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV) #26: FILE: drivers/gpu/drm/i915/intel_gpu_commands.h:199: +#define PIPE_CONTROL_TILE_CACHE_FLUSH (1<<28) /* gen11+ */ ^ total: 0 errors, 0 warnings, 2 checks, 81 lines checked _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
