From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Give names to the HSW/BDW SSKPD mask/shift values, give
and _SNB suffix to the SNB/IVB mask/shift values, and
drop the bogus non-mirrored SSKPD register define.
Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
---
drivers/gpu/drm/i915/i915_reg.h | 26 +++++++++++++++++---------
drivers/gpu/drm/i915/intel_pm.c | 20 ++++++++++----------
2 files changed, 27 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9dce09ed47f7..ea9a664980a6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3536,8 +3536,24 @@ enum i915_power_well_id {
#define MAD_DIMM_A_SIZE_SHIFT 0
#define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT)
-/* snb MCH registers for priority tuning */
#define MCH_SSKPD _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5d10)
+#define SSKPD_WM0_SHIFT_SNB 0
+#define SSKPD_WM1_SHIFT_SNB 8
+#define SSKPD_WM2_SHIFT_SNB 16
+#define SSKPD_WM3_SHIFT_SNB 24
+#define SSKPD_WM_MASK_SNB 0x3f
+#define SSKPD_NEW_WM0_SHIFT_HSW 56
+#define SSKPD_NEW_WM0_MASK_HSW 0xff
+#define SSKPD_OLD_WM0_SHIFT_HSW 0
+#define SSKPD_OLD_WM0_MASK_HSW 0xf
+#define SSKPD_WM1_SHIFT_HSW 4
+#define SSKPD_WM1_MASK_HSW 0xff
+#define SSKPD_WM2_SHIFT_HSW 12
+#define SSKPD_WM2_MASK_HSW 0xff
+#define SSKPD_WM3_SHIFT_HSW 20
+#define SSKPD_WM3_MASK_HSW 0x1ff
+#define SSKPD_WM4_SHIFT_HSW 32
+#define SSKPD_WM4_MASK_HSW 0x1ff
#define MCH_SECP_NRG_STTS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x592c)
@@ -6016,14 +6032,6 @@ enum {
#define ILK_SRLT_MASK 0x3f
-/* the address where we get all kinds of latency value */
-#define SSKPD _MMIO(0x5d10)
-#define SSKPD_WM_MASK 0x3f
-#define SSKPD_WM0_SHIFT 0
-#define SSKPD_WM1_SHIFT 8
-#define SSKPD_WM2_SHIFT 16
-#define SSKPD_WM3_SHIFT 24
-
/*
* The two pipe frame counter registers are not synchronized, so
* reading a stable value is somewhat tricky. The following code
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1a9ad431efbd..6ebde7bbac4e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2889,20 +2889,20 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
uint64_t sskpd = I915_READ64(MCH_SSKPD);
- wm[0] = (sskpd >> 56) & 0xFF;
+ wm[0] = (sskpd >> SSKPD_NEW_WM0_SHIFT_HSW) & SSKPD_NEW_WM0_MASK_HSW;
if (wm[0] == 0)
- wm[0] = sskpd & 0xF;
- wm[1] = (sskpd >> 4) & 0xFF;
- wm[2] = (sskpd >> 12) & 0xFF;
- wm[3] = (sskpd >> 20) & 0x1FF;
- wm[4] = (sskpd >> 32) & 0x1FF;
+ wm[0] = (sskpd >> SSKPD_OLD_WM0_SHIFT_HSW) & SSKPD_OLD_WM0_MASK_HSW;
+ wm[1] = (sskpd >> SSKPD_WM1_SHIFT_HSW) & SSKPD_WM1_MASK_HSW;
+ wm[2] = (sskpd >> SSKPD_WM2_SHIFT_HSW) & SSKPD_WM2_MASK_HSW;
+ wm[3] = (sskpd >> SSKPD_WM3_SHIFT_HSW) & SSKPD_WM3_MASK_HSW;
+ wm[4] = (sskpd >> SSKPD_WM4_SHIFT_HSW) & SSKPD_WM4_MASK_HSW;
} else if (INTEL_GEN(dev_priv) >= 6) {
uint32_t sskpd = I915_READ(MCH_SSKPD);
- wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
- wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
- wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
- wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
+ wm[0] = (sskpd >> SSKPD_WM0_SHIFT_SNB) & SSKPD_WM_MASK_SNB;
+ wm[1] = (sskpd >> SSKPD_WM1_SHIFT_SNB) & SSKPD_WM_MASK_SNB;
+ wm[2] = (sskpd >> SSKPD_WM2_SHIFT_SNB) & SSKPD_WM_MASK_SNB;
+ wm[3] = (sskpd >> SSKPD_WM3_SHIFT_SNB) & SSKPD_WM_MASK_SNB;
} else if (INTEL_GEN(dev_priv) >= 5) {
uint32_t mltr = I915_READ(MLTR_ILK);
--
2.18.1
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