From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
On ILK-IVB we must write the latency value read from SSKPD into
the latency field in the WM_LP registers. While bspec was never
clear on how the punit (or whatever) interprets these values
empirical evidence has shown that these are treated as a cookie
rather than as a literal latency value. That is, if we write a
value that we didn't get from SSKPD (just off by one is sufficient)
the system no longer appears to enter the corresponding power
saving state.
This was made much more obvious on HSW/BDW since there we longer
write the latency value into the WM_LP registers, and rather we
write the desired watermark level number (well, 2x the level
number).
Since we allow the user to adjust the latency values via debugfs,
and since we have some quirks where we adjust the values automagically,
we must stash away the originals read from SSKPD for later use
in the WM_LP registers.
Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
---
drivers/gpu/drm/i915/i915_drv.h | 6 ++++++
drivers/gpu/drm/i915/intel_pm.c | 37 +++++++++++++++++++++++----------
2 files changed, 32 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 95231f5f813d..c0204802d9cd 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1778,6 +1778,12 @@ struct drm_i915_private {
* (which we don't fully trust).
*/
bool distrust_bios_wm;
+
+ /*
+ * The values we must write to the LP watermark
+ * registers' latency field on ILK-BDW.
+ */
+ u16 ilk_wm_lp_latency[5];
} wm;
struct dram_info {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6328f0f8aa88..d5ad84be769d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3038,10 +3038,35 @@ static void snb_wm_lp3_irq_quirk(struct drm_i915_private *dev_priv)
intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
}
+/* The value we need to program into the WM_LPx latency field */
+static u16 ilk_wm_lp_latency(struct drm_i915_private *dev_priv, int level)
+{
+ if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
+ return 2 * level;
+ else
+ return dev_priv->wm.pri_latency[level];
+}
+
+static void ilk_setup_wm_lp_latency(struct drm_i915_private *dev_priv)
+{
+ int level, max_level = ilk_wm_max_level(dev_priv);
+
+ for (level = 1; level <= max_level; level++)
+ dev_priv->wm.ilk_wm_lp_latency[level] =
+ ilk_wm_lp_latency(dev_priv, level);
+}
+
static void ilk_setup_wm_latency(struct drm_i915_private *dev_priv)
{
intel_read_wm_latency(dev_priv, dev_priv->wm.pri_latency);
+ /*
+ * On ILK-IVB the values written to the LP watermark register
+ * latency field must match SSKPD 100%. So do this before any
+ * adjustments are made to the latency values we got from SSKPD.
+ */
+ ilk_setup_wm_lp_latency(dev_priv);
+
memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
sizeof(dev_priv->wm.pri_latency));
memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
@@ -3326,16 +3351,6 @@ static int ilk_wm_lp_to_level(int wm_lp, const struct ilk_pipe_wm *pipe_wm)
return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
}
-/* The value we need to program into the WM_LPx latency field */
-static unsigned int ilk_wm_lp_latency(struct drm_i915_private *dev_priv,
- int level)
-{
- if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
- return 2 * level;
- else
- return dev_priv->wm.pri_latency[level];
-}
-
static void ilk_compute_wm_results(struct drm_i915_private *dev_priv,
const struct ilk_pipe_wm *merged,
enum ilk_ddb_partitioning partitioning,
@@ -3360,7 +3375,7 @@ static void ilk_compute_wm_results(struct drm_i915_private *dev_priv,
* disabled. Doing otherwise could cause underruns.
*/
results->wm_lp[wm_lp - 1] =
- (ilk_wm_lp_latency(dev_priv, level) << WM1_LP_LATENCY_SHIFT) |
+ (dev_priv->wm.ilk_wm_lp_latency[level] << WM1_LP_LATENCY_SHIFT) |
(r->pri_val << WM1_LP_SR_SHIFT) |
r->cur_val;
--
2.18.1
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