Re: [PATCH v3 2/3] drm/i915: replace IS_GEN<N> with IS_GEN(..., N)

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On Wed, 05 Dec 2018, Lucas De Marchi <lucas.demarchi@xxxxxxxxx> wrote:
> Define IS_GEN() similarly to our IS_GEN_RANGE(). but use gen instead of
> gen_mask to do the comparison. Now callers can pass then gen as a parameter,
> so we don't require one macro for each gen.
>
> The following spatch was used to convert the users of these macros:
>
> @@
> expression e;
> @@
> (
> - IS_GEN2(e)
> + IS_GEN(e, 2)
> |
> - IS_GEN3(e)
> + IS_GEN(e, 3)
> |
> - IS_GEN4(e)
> + IS_GEN(e, 4)
> |
> - IS_GEN5(e)
> + IS_GEN(e, 5)
> |
> - IS_GEN6(e)
> + IS_GEN(e, 6)
> |
> - IS_GEN7(e)
> + IS_GEN(e, 7)
> |
> - IS_GEN8(e)
> + IS_GEN(e, 8)
> |
> - IS_GEN9(e)
> + IS_GEN(e, 9)
> |
> - IS_GEN10(e)
> + IS_GEN(e, 10)
> |
> - IS_GEN11(e)
> + IS_GEN(e, 11)
> )
>
> v2: use IS_GEN rather than GT_GEN and compare to info.gen rather than
>     using the bitmask
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@xxxxxxxxx>

I think the discussion on the IS_GEN() definition is slightly irrelevant
here, as this lets use trivially change it.

There's some potential follow-up work to change some of the IS_GEN(n) ||
IS_GEN(n + 1) uses to IS_GEN_RANGE(n, n + 1).

Anyway, I think this is the direction to go to, as the IS_GEN<N> macros
are getting a bit tedious.

Reviewed-by: Jani Nikula <jani.nikula@xxxxxxxxx>


> ---
>  drivers/gpu/drm/i915/gvt/vgpu.c            |  4 +-
>  drivers/gpu/drm/i915/i915_cmd_parser.c     |  2 +-
>  drivers/gpu/drm/i915/i915_debugfs.c        | 16 ++---
>  drivers/gpu/drm/i915/i915_drv.c            | 18 +++---
>  drivers/gpu/drm/i915/i915_drv.h            | 29 +++------
>  drivers/gpu/drm/i915/i915_gem.c            | 14 ++--
>  drivers/gpu/drm/i915/i915_gem_context.c    |  2 +-
>  drivers/gpu/drm/i915/i915_gem_execbuffer.c |  4 +-
>  drivers/gpu/drm/i915/i915_gem_fence_reg.c  | 10 +--
>  drivers/gpu/drm/i915/i915_gem_gtt.c        |  6 +-
>  drivers/gpu/drm/i915/i915_gem_stolen.c     |  7 +-
>  drivers/gpu/drm/i915/i915_gem_tiling.c     |  4 +-
>  drivers/gpu/drm/i915/i915_gpu_error.c      | 18 +++---
>  drivers/gpu/drm/i915/i915_irq.c            | 24 +++----
>  drivers/gpu/drm/i915/i915_perf.c           |  4 +-
>  drivers/gpu/drm/i915/i915_suspend.c        | 12 ++--
>  drivers/gpu/drm/i915/intel_atomic.c        |  2 +-
>  drivers/gpu/drm/i915/intel_audio.c         |  2 +-
>  drivers/gpu/drm/i915/intel_cdclk.c         | 10 +--
>  drivers/gpu/drm/i915/intel_crt.c           |  6 +-
>  drivers/gpu/drm/i915/intel_device_info.c   | 16 ++---
>  drivers/gpu/drm/i915/intel_display.c       | 74 +++++++++++-----------
>  drivers/gpu/drm/i915/intel_dp.c            | 24 +++----
>  drivers/gpu/drm/i915/intel_engine_cs.c     |  4 +-
>  drivers/gpu/drm/i915/intel_fbc.c           | 22 +++----
>  drivers/gpu/drm/i915/intel_fifo_underrun.c |  6 +-
>  drivers/gpu/drm/i915/intel_guc_fw.c        |  2 +-
>  drivers/gpu/drm/i915/intel_hangcheck.c     |  2 +-
>  drivers/gpu/drm/i915/intel_lrc.c           |  4 +-
>  drivers/gpu/drm/i915/intel_lvds.c          |  4 +-
>  drivers/gpu/drm/i915/intel_mocs.c          |  2 +-
>  drivers/gpu/drm/i915/intel_overlay.c       | 10 +--
>  drivers/gpu/drm/i915/intel_panel.c         |  8 +--
>  drivers/gpu/drm/i915/intel_pipe_crc.c      |  8 +--
>  drivers/gpu/drm/i915/intel_pm.c            | 60 +++++++++---------
>  drivers/gpu/drm/i915/intel_psr.c           |  4 +-
>  drivers/gpu/drm/i915/intel_ringbuffer.c    | 28 ++++----
>  drivers/gpu/drm/i915/intel_ringbuffer.h    |  4 +-
>  drivers/gpu/drm/i915/intel_runtime_pm.c    |  4 +-
>  drivers/gpu/drm/i915/intel_sprite.c        |  6 +-
>  drivers/gpu/drm/i915/intel_uc.c            |  2 +-
>  drivers/gpu/drm/i915/intel_uncore.c        | 18 +++---
>  drivers/gpu/drm/i915/intel_wopcm.c         |  4 +-
>  drivers/gpu/drm/i915/intel_workarounds.c   |  4 +-
>  44 files changed, 251 insertions(+), 263 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c
> index c628be05fbfe..e1c860f80eb0 100644
> --- a/drivers/gpu/drm/i915/gvt/vgpu.c
> +++ b/drivers/gpu/drm/i915/gvt/vgpu.c
> @@ -148,10 +148,10 @@ int intel_gvt_init_vgpu_types(struct intel_gvt *gvt)
>  		gvt->types[i].avail_instance = min(low_avail / vgpu_types[i].low_mm,
>  						   high_avail / vgpu_types[i].high_mm);
>  
> -		if (IS_GEN8(gvt->dev_priv))
> +		if (IS_GEN(gvt->dev_priv, 8))
>  			sprintf(gvt->types[i].name, "GVTg_V4_%s",
>  						vgpu_types[i].name);
> -		else if (IS_GEN9(gvt->dev_priv))
> +		else if (IS_GEN(gvt->dev_priv, 9))
>  			sprintf(gvt->types[i].name, "GVTg_V5_%s",
>  						vgpu_types[i].name);
>  
> diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
> index 95478db9998b..33e8eed64423 100644
> --- a/drivers/gpu/drm/i915/i915_cmd_parser.c
> +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
> @@ -865,7 +865,7 @@ void intel_engine_init_cmd_parser(struct intel_engine_cs *engine)
>  	int cmd_table_count;
>  	int ret;
>  
> -	if (!IS_GEN7(engine->i915))
> +	if (!IS_GEN(engine->i915, 7))
>  		return;
>  
>  	switch (engine->id) {
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 38dcee1ca062..53e3f57a13f3 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1064,7 +1064,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
>  
>  	intel_runtime_pm_get(dev_priv);
>  
> -	if (IS_GEN5(dev_priv)) {
> +	if (IS_GEN(dev_priv, 5)) {
>  		u16 rgvswctl = I915_READ16(MEMSWCTL);
>  		u16 rgvstat = I915_READ16(MEMSTAT_ILK);
>  
> @@ -1785,7 +1785,7 @@ static int i915_emon_status(struct seq_file *m, void *unused)
>  	unsigned long temp, chipset, gfx;
>  	int ret;
>  
> -	if (!IS_GEN5(dev_priv))
> +	if (!IS_GEN(dev_priv, 5))
>  		return -ENODEV;
>  
>  	intel_runtime_pm_get(dev_priv);
> @@ -2034,7 +2034,7 @@ static int i915_swizzle_info(struct seq_file *m, void *data)
>  	seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
>  		   swizzle_string(dev_priv->mm.bit_6_swizzle_y));
>  
> -	if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv)) {
> +	if (IS_GEN(dev_priv, 3) || IS_GEN(dev_priv, 4)) {
>  		seq_printf(m, "DDC = 0x%08x\n",
>  			   I915_READ(DCC));
>  		seq_printf(m, "DDC2 = 0x%08x\n",
> @@ -2119,12 +2119,12 @@ static void gen6_ppgtt_info(struct seq_file *m,
>  	struct intel_engine_cs *engine;
>  	enum intel_engine_id id;
>  
> -	if (IS_GEN6(dev_priv))
> +	if (IS_GEN(dev_priv, 6))
>  		seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
>  
>  	for_each_engine(engine, dev_priv, id) {
>  		seq_printf(m, "%s\n", engine->name);
> -		if (IS_GEN7(dev_priv))
> +		if (IS_GEN(dev_priv, 7))
>  			seq_printf(m, "GFX_MODE: 0x%08x\n",
>  				   I915_READ(RING_MODE_GEN7(engine)));
>  		seq_printf(m, "PP_DIR_BASE: 0x%08x\n",
> @@ -4268,7 +4268,7 @@ i915_cache_sharing_get(void *data, u64 *val)
>  	struct drm_i915_private *dev_priv = data;
>  	u32 snpcr;
>  
> -	if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))
> +	if (!(IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7)))
>  		return -ENODEV;
>  
>  	intel_runtime_pm_get(dev_priv);
> @@ -4288,7 +4288,7 @@ i915_cache_sharing_set(void *data, u64 val)
>  	struct drm_i915_private *dev_priv = data;
>  	u32 snpcr;
>  
> -	if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))
> +	if (!(IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7)))
>  		return -ENODEV;
>  
>  	if (val > 3)
> @@ -4545,7 +4545,7 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
>  		cherryview_sseu_device_status(dev_priv, &sseu);
>  	} else if (IS_BROADWELL(dev_priv)) {
>  		broadwell_sseu_device_status(dev_priv, &sseu);
> -	} else if (IS_GEN9(dev_priv)) {
> +	} else if (IS_GEN(dev_priv, 9)) {
>  		gen9_sseu_device_status(dev_priv, &sseu);
>  	} else if (INTEL_GEN(dev_priv) >= 10) {
>  		gen10_sseu_device_status(dev_priv, &sseu);
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index b310a897a4ad..77c0f97fe77c 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -132,15 +132,15 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
>  	switch (id) {
>  	case INTEL_PCH_IBX_DEVICE_ID_TYPE:
>  		DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
> -		WARN_ON(!IS_GEN5(dev_priv));
> +		WARN_ON(!IS_GEN(dev_priv, 5));
>  		return PCH_IBX;
>  	case INTEL_PCH_CPT_DEVICE_ID_TYPE:
>  		DRM_DEBUG_KMS("Found CougarPoint PCH\n");
> -		WARN_ON(!IS_GEN6(dev_priv) && !IS_IVYBRIDGE(dev_priv));
> +		WARN_ON(!IS_GEN(dev_priv, 6) && !IS_IVYBRIDGE(dev_priv));
>  		return PCH_CPT;
>  	case INTEL_PCH_PPT_DEVICE_ID_TYPE:
>  		DRM_DEBUG_KMS("Found PantherPoint PCH\n");
> -		WARN_ON(!IS_GEN6(dev_priv) && !IS_IVYBRIDGE(dev_priv));
> +		WARN_ON(!IS_GEN(dev_priv, 6) && !IS_IVYBRIDGE(dev_priv));
>  		/* PantherPoint is CPT compatible */
>  		return PCH_CPT;
>  	case INTEL_PCH_LPT_DEVICE_ID_TYPE:
> @@ -217,9 +217,9 @@ intel_virt_detect_pch(const struct drm_i915_private *dev_priv)
>  	 * make an educated guess as to which PCH is really there.
>  	 */
>  
> -	if (IS_GEN5(dev_priv))
> +	if (IS_GEN(dev_priv, 5))
>  		id = INTEL_PCH_IBX_DEVICE_ID_TYPE;
> -	else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
> +	else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
>  		id = INTEL_PCH_CPT_DEVICE_ID_TYPE;
>  	else if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
>  		id = INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
> @@ -966,7 +966,7 @@ static int i915_mmio_setup(struct drm_i915_private *dev_priv)
>  	int mmio_bar;
>  	int mmio_size;
>  
> -	mmio_bar = IS_GEN2(dev_priv) ? 1 : 0;
> +	mmio_bar = IS_GEN(dev_priv, 2) ? 1 : 0;
>  	/*
>  	 * Before gen4, the registers and the GTT are behind different BARs.
>  	 * However, from gen4 onwards, the registers and the GTT are shared
> @@ -1341,7 +1341,7 @@ intel_get_dram_info(struct drm_i915_private *dev_priv)
>  	/* Need to calculate bandwidth only for Gen9 */
>  	if (IS_BROXTON(dev_priv))
>  		ret = bxt_get_dram_info(dev_priv);
> -	else if (IS_GEN9(dev_priv))
> +	else if (IS_GEN(dev_priv, 9))
>  		ret = skl_get_dram_info(dev_priv);
>  	else
>  		ret = skl_dram_get_channels_info(dev_priv);
> @@ -1436,7 +1436,7 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
>  	pci_set_master(pdev);
>  
>  	/* overlay on gen2 is broken and can't address above 1G */
> -	if (IS_GEN2(dev_priv)) {
> +	if (IS_GEN(dev_priv, 2)) {
>  		ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
>  		if (ret) {
>  			DRM_ERROR("failed to set DMA mask\n");
> @@ -1574,7 +1574,7 @@ static void i915_driver_register(struct drm_i915_private *dev_priv)
>  		acpi_video_register();
>  	}
>  
> -	if (IS_GEN5(dev_priv))
> +	if (IS_GEN(dev_priv, 5))
>  		intel_gpu_ips_init(dev_priv);
>  
>  	intel_audio_init(dev_priv);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index affcb028ff8d..660d35aed20f 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2216,6 +2216,10 @@ intel_info(const struct drm_i915_private *dev_priv)
>  #define IS_GEN_RANGE(dev_priv, s, e) \
>  	(!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e))))
>  
> +#define IS_GEN(dev_priv, n) \
> +	(BUILD_BUG_ON_ZERO(!__builtin_constant_p(n)) + \
> +	 (dev_priv)->info.gen == (n))
> +
>  /*
>   * Return true if revision is in range [since,until] inclusive.
>   *
> @@ -2367,26 +2371,9 @@ intel_info(const struct drm_i915_private *dev_priv)
>  #define IS_ICL_REVID(p, since, until) \
>  	(IS_ICELAKE(p) && IS_REVID(p, since, until))
>  
> -/*
> - * The genX designation typically refers to the render engine, so render
> - * capability related checks should use IS_GEN, while display and other checks
> - * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
> - * chips, etc.).
> - */
> -#define IS_GEN2(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(1)))
> -#define IS_GEN3(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(2)))
> -#define IS_GEN4(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(3)))
> -#define IS_GEN5(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(4)))
> -#define IS_GEN6(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(5)))
> -#define IS_GEN7(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(6)))
> -#define IS_GEN8(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(7)))
> -#define IS_GEN9(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(8)))
> -#define IS_GEN10(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(9)))
> -#define IS_GEN11(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(10)))
> -
>  #define IS_LP(dev_priv)	(INTEL_INFO(dev_priv)->is_lp)
> -#define IS_GEN9_LP(dev_priv)	(IS_GEN9(dev_priv) && IS_LP(dev_priv))
> -#define IS_GEN9_BC(dev_priv)	(IS_GEN9(dev_priv) && !IS_LP(dev_priv))
> +#define IS_GEN9_LP(dev_priv)	(IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
> +#define IS_GEN9_BC(dev_priv)	(IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
>  
>  #define ENGINE_MASK(id)	BIT(id)
>  #define RENDER_RING	ENGINE_MASK(RCS)
> @@ -2407,7 +2394,7 @@ intel_info(const struct drm_i915_private *dev_priv)
>  #define HAS_BLT(dev_priv)	HAS_ENGINE(dev_priv, BCS)
>  #define HAS_VEBOX(dev_priv)	HAS_ENGINE(dev_priv, VECS)
>  
> -#define HAS_LEGACY_SEMAPHORES(dev_priv) IS_GEN7(dev_priv)
> +#define HAS_LEGACY_SEMAPHORES(dev_priv) IS_GEN(dev_priv, 7)
>  
>  #define HAS_LLC(dev_priv)	((dev_priv)->info.has_llc)
>  #define HAS_SNOOP(dev_priv)	((dev_priv)->info.has_snoop)
> @@ -2459,7 +2446,7 @@ intel_info(const struct drm_i915_private *dev_priv)
>  /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
>   * rows, which changed the alignment requirements and fence programming.
>   */
> -#define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \
> +#define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN(dev_priv, 2) && \
>  					 !(IS_I915G(dev_priv) || \
>  					 IS_I915GM(dev_priv)))
>  #define SUPPORTS_TV(dev_priv)		((dev_priv)->info.display.supports_tv)
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index d36a9755ad91..39ee67e01bb7 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -5226,15 +5226,15 @@ void i915_gem_init_swizzling(struct drm_i915_private *dev_priv)
>  	I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
>  				 DISP_TILE_SURFACE_SWIZZLING);
>  
> -	if (IS_GEN5(dev_priv))
> +	if (IS_GEN(dev_priv, 5))
>  		return;
>  
>  	I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
> -	if (IS_GEN6(dev_priv))
> +	if (IS_GEN(dev_priv, 6))
>  		I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
> -	else if (IS_GEN7(dev_priv))
> +	else if (IS_GEN(dev_priv, 7))
>  		I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
> -	else if (IS_GEN8(dev_priv))
> +	else if (IS_GEN(dev_priv, 8))
>  		I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
>  	else
>  		BUG();
> @@ -5256,10 +5256,10 @@ static void init_unused_rings(struct drm_i915_private *dev_priv)
>  		init_unused_ring(dev_priv, SRB1_BASE);
>  		init_unused_ring(dev_priv, SRB2_BASE);
>  		init_unused_ring(dev_priv, SRB3_BASE);
> -	} else if (IS_GEN2(dev_priv)) {
> +	} else if (IS_GEN(dev_priv, 2)) {
>  		init_unused_ring(dev_priv, SRB0_BASE);
>  		init_unused_ring(dev_priv, SRB1_BASE);
> -	} else if (IS_GEN3(dev_priv)) {
> +	} else if (IS_GEN(dev_priv, 3)) {
>  		init_unused_ring(dev_priv, PRB1_BASE);
>  		init_unused_ring(dev_priv, PRB2_BASE);
>  	}
> @@ -5583,7 +5583,7 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
>  	}
>  
>  	ret = i915_gem_init_scratch(dev_priv,
> -				    IS_GEN2(dev_priv) ? SZ_256K : PAGE_SIZE);
> +				    IS_GEN(dev_priv, 2) ? SZ_256K : PAGE_SIZE);
>  	if (ret) {
>  		GEM_BUG_ON(ret == -EIO);
>  		goto err_ggtt;
> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
> index 371c07087095..014152e2bc68 100644
> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> @@ -311,7 +311,7 @@ static u32 default_desc_template(const struct drm_i915_private *i915,
>  		address_mode = INTEL_LEGACY_64B_CONTEXT;
>  	desc |= address_mode << GEN8_CTX_ADDRESSING_MODE_SHIFT;
>  
> -	if (IS_GEN8(i915))
> +	if (IS_GEN(i915, 8))
>  		desc |= GEN8_CTX_L3LLC_COHERENT;
>  
>  	/* TODO: WaDisableLiteRestore when we start using semaphore
> diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> index 10a4afb4f235..eb26f4817fce 100644
> --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> @@ -1385,7 +1385,7 @@ eb_relocate_entry(struct i915_execbuffer *eb,
>  		 * batchbuffers.
>  		 */
>  		if (reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION &&
> -		    IS_GEN6(eb->i915)) {
> +		    IS_GEN(eb->i915, 6)) {
>  			err = i915_vma_bind(target, target->obj->cache_level,
>  					    PIN_GLOBAL);
>  			if (WARN_ONCE(err,
> @@ -1898,7 +1898,7 @@ static int i915_reset_gen7_sol_offsets(struct i915_request *rq)
>  	u32 *cs;
>  	int i;
>  
> -	if (!IS_GEN7(rq->i915) || rq->engine->id != RCS) {
> +	if (!IS_GEN(rq->i915, 7) || rq->engine->id != RCS) {
>  		DRM_DEBUG("sol reset is gen7/rcs only\n");
>  		return -EINVAL;
>  	}
> diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
> index d548ac05ccd7..24df2e2a8fc1 100644
> --- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c
> +++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
> @@ -193,9 +193,9 @@ static void fence_write(struct drm_i915_fence_reg *fence,
>  	 * and explicitly managed for internal users.
>  	 */
>  
> -	if (IS_GEN2(fence->i915))
> +	if (IS_GEN(fence->i915, 2))
>  		i830_write_fence_reg(fence, vma);
> -	else if (IS_GEN3(fence->i915))
> +	else if (IS_GEN(fence->i915, 3))
>  		i915_write_fence_reg(fence, vma);
>  	else
>  		i965_write_fence_reg(fence, vma);
> @@ -596,13 +596,13 @@ i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv)
>  				swizzle_y = I915_BIT_6_SWIZZLE_NONE;
>  			}
>  		}
> -	} else if (IS_GEN5(dev_priv)) {
> +	} else if (IS_GEN(dev_priv, 5)) {
>  		/* On Ironlake whatever DRAM config, GPU always do
>  		 * same swizzling setup.
>  		 */
>  		swizzle_x = I915_BIT_6_SWIZZLE_9_10;
>  		swizzle_y = I915_BIT_6_SWIZZLE_9;
> -	} else if (IS_GEN2(dev_priv)) {
> +	} else if (IS_GEN(dev_priv, 2)) {
>  		/* As far as we know, the 865 doesn't have these bit 6
>  		 * swizzling issues.
>  		 */
> @@ -647,7 +647,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv)
>  		}
>  
>  		/* check for L-shaped memory aka modified enhanced addressing */
> -		if (IS_GEN4(dev_priv) &&
> +		if (IS_GEN(dev_priv, 4) &&
>  		    !(I915_READ(DCC2) & DCC2_MODIFIED_ENHANCED_DISABLE)) {
>  			swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
>  			swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index add1fe7aeb93..609c2fd1ea36 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -2195,9 +2195,9 @@ int i915_ppgtt_init_hw(struct drm_i915_private *dev_priv)
>  {
>  	gtt_write_workarounds(dev_priv);
>  
> -	if (IS_GEN6(dev_priv))
> +	if (IS_GEN(dev_priv, 6))
>  		gen6_ppgtt_enable(dev_priv);
> -	else if (IS_GEN7(dev_priv))
> +	else if (IS_GEN(dev_priv, 7))
>  		gen7_ppgtt_enable(dev_priv);
>  
>  	return 0;
> @@ -2279,7 +2279,7 @@ static bool needs_idle_maps(struct drm_i915_private *dev_priv)
>  	/* Query intel_iommu to see if we need the workaround. Presumably that
>  	 * was loaded first.
>  	 */
> -	return IS_GEN5(dev_priv) && IS_MOBILE(dev_priv) && intel_vtd_active();
> +	return IS_GEN(dev_priv, 5) && IS_MOBILE(dev_priv) && intel_vtd_active();
>  }
>  
>  static void gen6_check_faults(struct drm_i915_private *dev_priv)
> diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c
> index f29a7ff7c362..2f756a97689a 100644
> --- a/drivers/gpu/drm/i915/i915_gem_stolen.c
> +++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
> @@ -102,7 +102,7 @@ static int i915_adjust_stolen(struct drm_i915_private *dev_priv,
>  		resource_size_t ggtt_start;
>  
>  		ggtt_start = I915_READ(PGTBL_CTL);
> -		if (IS_GEN4(dev_priv))
> +		if (IS_GEN(dev_priv, 4))
>  			ggtt_start = (ggtt_start & PGTBL_ADDRESS_LO_MASK) |
>  				     (ggtt_start & PGTBL_ADDRESS_HI_MASK) << 28;
>  		else
> @@ -156,7 +156,7 @@ static int i915_adjust_stolen(struct drm_i915_private *dev_priv,
>  		 * GEN3 firmware likes to smash pci bridges into the stolen
>  		 * range. Apparently this works.
>  		 */
> -		if (r == NULL && !IS_GEN3(dev_priv)) {
> +		if (r == NULL && !IS_GEN(dev_priv, 3)) {
>  			DRM_ERROR("conflict detected with stolen region: %pR\n",
>  				  dsm);
>  
> @@ -194,7 +194,8 @@ static void g4x_get_stolen_reserved(struct drm_i915_private *dev_priv,
>  	 * Whether ILK really reuses the ELK register for this is unclear.
>  	 * Let's see if we catch anyone with this supposedly enabled on ILK.
>  	 */
> -	WARN(IS_GEN5(dev_priv), "ILK stolen reserved found? 0x%08x\n", reg_val);
> +	WARN(IS_GEN(dev_priv, 5), "ILK stolen reserved found? 0x%08x\n",
> +	     reg_val);
>  
>  	if (!(reg_val & G4X_STOLEN_RESERVED_ADDR2_MASK))
>  		return;
> diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
> index d9dc9df523b5..39319ff1679c 100644
> --- a/drivers/gpu/drm/i915/i915_gem_tiling.c
> +++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
> @@ -87,7 +87,7 @@ u32 i915_gem_fence_size(struct drm_i915_private *i915,
>  	}
>  
>  	/* Previous chips need a power-of-two fence region when tiling */
> -	if (IS_GEN3(i915))
> +	if (IS_GEN(i915, 3))
>  		ggtt_size = 1024*1024;
>  	else
>  		ggtt_size = 512*1024;
> @@ -162,7 +162,7 @@ i915_tiling_ok(struct drm_i915_gem_object *obj,
>  			return false;
>  	}
>  
> -	if (IS_GEN2(i915) ||
> +	if (IS_GEN(i915, 2) ||
>  	    (tiling == I915_TILING_Y && HAS_128_BYTE_Y_TILING(i915)))
>  		tile_width = 128;
>  	else
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
> index 07465123c166..ccfd91c72477 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -735,7 +735,7 @@ static void __err_print_to_sgl(struct drm_i915_error_state_buf *m,
>  		err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
>  	}
>  
> -	if (IS_GEN7(m->i915))
> +	if (IS_GEN(m->i915, 7))
>  		err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
>  
>  	for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
> @@ -1314,7 +1314,7 @@ static void error_record_engine_registers(struct i915_gpu_state *error,
>  	if (!HWS_NEEDS_PHYSICAL(dev_priv)) {
>  		i915_reg_t mmio;
>  
> -		if (IS_GEN7(dev_priv)) {
> +		if (IS_GEN(dev_priv, 7)) {
>  			switch (engine->id) {
>  			default:
>  			case RCS:
> @@ -1330,7 +1330,7 @@ static void error_record_engine_registers(struct i915_gpu_state *error,
>  				mmio = VEBOX_HWS_PGA_GEN7;
>  				break;
>  			}
> -		} else if (IS_GEN6(engine->i915)) {
> +		} else if (IS_GEN(engine->i915, 6)) {
>  			mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
>  		} else {
>  			/* XXX: gen8 returns to sanity */
> @@ -1352,10 +1352,10 @@ static void error_record_engine_registers(struct i915_gpu_state *error,
>  
>  		ee->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(engine));
>  
> -		if (IS_GEN6(dev_priv))
> +		if (IS_GEN(dev_priv, 6))
>  			ee->vm_info.pp_dir_base =
>  				I915_READ(RING_PP_DIR_BASE_READ(engine));
> -		else if (IS_GEN7(dev_priv))
> +		else if (IS_GEN(dev_priv, 7))
>  			ee->vm_info.pp_dir_base =
>  				I915_READ(RING_PP_DIR_BASE(engine));
>  		else if (INTEL_GEN(dev_priv) >= 8)
> @@ -1725,7 +1725,7 @@ static void capture_reg_state(struct i915_gpu_state *error)
>  		error->forcewake = I915_READ_FW(FORCEWAKE_VLV);
>  	}
>  
> -	if (IS_GEN7(dev_priv))
> +	if (IS_GEN(dev_priv, 7))
>  		error->err_int = I915_READ(GEN7_ERR_INT);
>  
>  	if (INTEL_GEN(dev_priv) >= 8) {
> @@ -1733,7 +1733,7 @@ static void capture_reg_state(struct i915_gpu_state *error)
>  		error->fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1);
>  	}
>  
> -	if (IS_GEN6(dev_priv)) {
> +	if (IS_GEN(dev_priv, 6)) {
>  		error->forcewake = I915_READ_FW(FORCEWAKE);
>  		error->gab_ctl = I915_READ(GAB_CTL);
>  		error->gfx_mode = I915_READ(GFX_MODE);
> @@ -1753,7 +1753,7 @@ static void capture_reg_state(struct i915_gpu_state *error)
>  		error->ccid = I915_READ(CCID);
>  
>  	/* 3: Feature specific registers */
> -	if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
> +	if (IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7)) {
>  		error->gam_ecochk = I915_READ(GAM_ECOCHK);
>  		error->gac_eco = I915_READ(GAC_ECO_BITS);
>  	}
> @@ -1777,7 +1777,7 @@ static void capture_reg_state(struct i915_gpu_state *error)
>  		error->ier = I915_READ(DEIER);
>  		error->gtier[0] = I915_READ(GTIER);
>  		error->ngtier = 1;
> -	} else if (IS_GEN2(dev_priv)) {
> +	} else if (IS_GEN(dev_priv, 2)) {
>  		error->ier = I915_READ16(IER);
>  	} else if (!IS_VALLEYVIEW(dev_priv)) {
>  		error->ier = I915_READ(IER);
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index d447d7d508f4..e2dac9b5f4ce 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -950,7 +950,7 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
>  	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
>  		vtotal /= 2;
>  
> -	if (IS_GEN2(dev_priv))
> +	if (IS_GEN(dev_priv, 2))
>  		position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
>  	else
>  		position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
> @@ -1030,7 +1030,7 @@ static bool i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
>  	if (stime)
>  		*stime = ktime_get();
>  
> -	if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
> +	if (IS_GEN(dev_priv, 2) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
>  		/* No obvious pixelcount register. Only query vertical
>  		 * scanout position from Display scan line register.
>  		 */
> @@ -1090,7 +1090,7 @@ static bool i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
>  	else
>  		position += vtotal - vbl_end;
>  
> -	if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
> +	if (IS_GEN(dev_priv, 2) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
>  		*vpos = position;
>  		*hpos = 0;
>  	} else {
> @@ -2547,7 +2547,7 @@ static void ilk_display_irq_handler(struct drm_i915_private *dev_priv,
>  		I915_WRITE(SDEIIR, pch_iir);
>  	}
>  
> -	if (IS_GEN5(dev_priv) && de_iir & DE_PCU_EVENT)
> +	if (IS_GEN(dev_priv, 5) && de_iir & DE_PCU_EVENT)
>  		ironlake_rps_change_irq_handler(dev_priv);
>  }
>  
> @@ -3243,7 +3243,7 @@ void i915_clear_error_registers(struct drm_i915_private *dev_priv)
>  {
>  	u32 eir;
>  
> -	if (!IS_GEN2(dev_priv))
> +	if (!IS_GEN(dev_priv, 2))
>  		I915_WRITE(PGTBL_ER, I915_READ(PGTBL_ER));
>  
>  	if (INTEL_GEN(dev_priv) < 4)
> @@ -3586,11 +3586,11 @@ static void ironlake_irq_reset(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  
> -	if (IS_GEN5(dev_priv))
> +	if (IS_GEN(dev_priv, 5))
>  		I915_WRITE(HWSTAM, 0xffffffff);
>  
>  	GEN3_IRQ_RESET(DE);
> -	if (IS_GEN7(dev_priv))
> +	if (IS_GEN(dev_priv, 7))
>  		I915_WRITE(GEN7_ERR_INT, 0xffffffff);
>  
>  	if (IS_HASWELL(dev_priv)) {
> @@ -4045,7 +4045,7 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev)
>  	}
>  
>  	gt_irqs |= GT_RENDER_USER_INTERRUPT;
> -	if (IS_GEN5(dev_priv)) {
> +	if (IS_GEN(dev_priv, 5)) {
>  		gt_irqs |= ILK_BSD_USER_INTERRUPT;
>  	} else {
>  		gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
> @@ -4836,7 +4836,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
>  	if (INTEL_GEN(dev_priv) >= 8)
>  		rps->pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC;
>  
> -	if (IS_GEN2(dev_priv)) {
> +	if (IS_GEN(dev_priv, 2)) {
>  		/* Gen2 doesn't have a hardware frame counter */
>  		dev->max_vblank_count = 0;
>  	} else if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
> @@ -4852,7 +4852,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
>  	 * Gen2 doesn't have a hardware frame counter and so depends on
>  	 * vblank interrupts to produce sane vblank seuquence numbers.
>  	 */
> -	if (!IS_GEN2(dev_priv))
> +	if (!IS_GEN(dev_priv, 2))
>  		dev->vblank_disable_immediate = true;
>  
>  	/* Most platforms treat the display irq block as an always-on
> @@ -4924,14 +4924,14 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
>  		dev->driver->disable_vblank = ironlake_disable_vblank;
>  		dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
>  	} else {
> -		if (IS_GEN2(dev_priv)) {
> +		if (IS_GEN(dev_priv, 2)) {
>  			dev->driver->irq_preinstall = i8xx_irq_reset;
>  			dev->driver->irq_postinstall = i8xx_irq_postinstall;
>  			dev->driver->irq_handler = i8xx_irq_handler;
>  			dev->driver->irq_uninstall = i8xx_irq_reset;
>  			dev->driver->enable_vblank = i8xx_enable_vblank;
>  			dev->driver->disable_vblank = i8xx_disable_vblank;
> -		} else if (IS_GEN3(dev_priv)) {
> +		} else if (IS_GEN(dev_priv, 3)) {
>  			dev->driver->irq_preinstall = i915_irq_reset;
>  			dev->driver->irq_postinstall = i915_irq_postinstall;
>  			dev->driver->irq_uninstall = i915_irq_reset;
> diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
> index ad0095be435d..6c7992320443 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -3415,7 +3415,7 @@ void i915_perf_init(struct drm_i915_private *dev_priv)
>  		dev_priv->perf.oa.ops.read = gen8_oa_read;
>  		dev_priv->perf.oa.ops.oa_hw_tail_read = gen8_oa_hw_tail_read;
>  
> -		if (IS_GEN8(dev_priv) || IS_GEN9(dev_priv)) {
> +		if (IS_GEN(dev_priv, 8) || IS_GEN(dev_priv, 9)) {
>  			dev_priv->perf.oa.ops.is_valid_b_counter_reg =
>  				gen7_is_valid_b_counter_addr;
>  			dev_priv->perf.oa.ops.is_valid_mux_reg =
> @@ -3431,7 +3431,7 @@ void i915_perf_init(struct drm_i915_private *dev_priv)
>  			dev_priv->perf.oa.ops.enable_metric_set = gen8_enable_metric_set;
>  			dev_priv->perf.oa.ops.disable_metric_set = gen8_disable_metric_set;
>  
> -			if (IS_GEN8(dev_priv)) {
> +			if (IS_GEN(dev_priv, 8)) {
>  				dev_priv->perf.oa.ctx_oactxctrl_offset = 0x120;
>  				dev_priv->perf.oa.ctx_flexeu0_offset = 0x2ce;
>  
> diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
> index 8f3aa4dc0c98..f40ba5e429e0 100644
> --- a/drivers/gpu/drm/i915/i915_suspend.c
> +++ b/drivers/gpu/drm/i915/i915_suspend.c
> @@ -65,7 +65,7 @@ int i915_save_state(struct drm_i915_private *dev_priv)
>  
>  	i915_save_display(dev_priv);
>  
> -	if (IS_GEN4(dev_priv))
> +	if (IS_GEN(dev_priv, 4))
>  		pci_read_config_word(pdev, GCDGMBUS,
>  				     &dev_priv->regfile.saveGCDGMBUS);
>  
> @@ -77,14 +77,14 @@ int i915_save_state(struct drm_i915_private *dev_priv)
>  	dev_priv->regfile.saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
>  
>  	/* Scratch space */
> -	if (IS_GEN2(dev_priv) && IS_MOBILE(dev_priv)) {
> +	if (IS_GEN(dev_priv, 2) && IS_MOBILE(dev_priv)) {
>  		for (i = 0; i < 7; i++) {
>  			dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i));
>  			dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
>  		}
>  		for (i = 0; i < 3; i++)
>  			dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i));
> -	} else if (IS_GEN2(dev_priv)) {
> +	} else if (IS_GEN(dev_priv, 2)) {
>  		for (i = 0; i < 7; i++)
>  			dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
>  	} else if (HAS_GMCH_DISPLAY(dev_priv)) {
> @@ -108,7 +108,7 @@ int i915_restore_state(struct drm_i915_private *dev_priv)
>  
>  	mutex_lock(&dev_priv->drm.struct_mutex);
>  
> -	if (IS_GEN4(dev_priv))
> +	if (IS_GEN(dev_priv, 4))
>  		pci_write_config_word(pdev, GCDGMBUS,
>  				      dev_priv->regfile.saveGCDGMBUS);
>  	i915_restore_display(dev_priv);
> @@ -122,14 +122,14 @@ int i915_restore_state(struct drm_i915_private *dev_priv)
>  	I915_WRITE(MI_ARB_STATE, dev_priv->regfile.saveMI_ARB_STATE | 0xffff0000);
>  
>  	/* Scratch space */
> -	if (IS_GEN2(dev_priv) && IS_MOBILE(dev_priv)) {
> +	if (IS_GEN(dev_priv, 2) && IS_MOBILE(dev_priv)) {
>  		for (i = 0; i < 7; i++) {
>  			I915_WRITE(SWF0(i), dev_priv->regfile.saveSWF0[i]);
>  			I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
>  		}
>  		for (i = 0; i < 3; i++)
>  			I915_WRITE(SWF3(i), dev_priv->regfile.saveSWF3[i]);
> -	} else if (IS_GEN2(dev_priv)) {
> +	} else if (IS_GEN(dev_priv, 2)) {
>  		for (i = 0; i < 7; i++)
>  			I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
>  	} else if (HAS_GMCH_DISPLAY(dev_priv)) {
> diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c
> index 8cb02f28d30c..fdfc7425e644 100644
> --- a/drivers/gpu/drm/i915/intel_atomic.c
> +++ b/drivers/gpu/drm/i915/intel_atomic.c
> @@ -233,7 +233,7 @@ static void intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_sta
>  	if (plane_state && plane_state->base.fb &&
>  	    plane_state->base.fb->format->is_yuv &&
>  	    plane_state->base.fb->format->num_planes > 1) {
> -		if (IS_GEN9(dev_priv) &&
> +		if (IS_GEN(dev_priv, 9) &&
>  		    !IS_GEMINILAKE(dev_priv)) {
>  			mode = SKL_PS_SCALER_MODE_NV12;
>  		} else if (icl_is_hdr_plane(to_intel_plane(plane_state->base.plane))) {
> diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
> index ae55a6865d5c..0571aa2846a7 100644
> --- a/drivers/gpu/drm/i915/intel_audio.c
> +++ b/drivers/gpu/drm/i915/intel_audio.c
> @@ -758,7 +758,7 @@ static void i915_audio_component_codec_wake_override(struct device *kdev,
>  	struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
>  	u32 tmp;
>  
> -	if (!IS_GEN9(dev_priv))
> +	if (!IS_GEN(dev_priv, 9))
>  		return;
>  
>  	i915_audio_component_get_power(kdev);
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> index 25e3aba9cded..2021e484a287 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -2140,7 +2140,7 @@ static int intel_pixel_rate_to_cdclk(struct drm_i915_private *dev_priv,
>  {
>  	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
>  		return DIV_ROUND_UP(pixel_rate, 2);
> -	else if (IS_GEN9(dev_priv) ||
> +	else if (IS_GEN(dev_priv, 9) ||
>  		 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
>  		return pixel_rate;
>  	else if (IS_CHERRYVIEW(dev_priv))
> @@ -2176,7 +2176,7 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
>  		if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
>  			/* Display WA #1145: glk,cnl */
>  			min_cdclk = max(316800, min_cdclk);
> -		} else if (IS_GEN9(dev_priv) || IS_BROADWELL(dev_priv)) {
> +		} else if (IS_GEN(dev_priv, 9) || IS_BROADWELL(dev_priv)) {
>  			/* Display WA #1144: skl,bxt */
>  			min_cdclk = max(432000, min_cdclk);
>  		}
> @@ -2537,7 +2537,7 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
>  
>  	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
>  		return 2 * max_cdclk_freq;
> -	else if (IS_GEN9(dev_priv) ||
> +	else if (IS_GEN(dev_priv, 9) ||
>  		 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
>  		return max_cdclk_freq;
>  	else if (IS_CHERRYVIEW(dev_priv))
> @@ -2785,9 +2785,9 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
>  		dev_priv->display.get_cdclk = hsw_get_cdclk;
>  	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>  		dev_priv->display.get_cdclk = vlv_get_cdclk;
> -	else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
> +	else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
>  		dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
> -	else if (IS_GEN5(dev_priv))
> +	else if (IS_GEN(dev_priv, 5))
>  		dev_priv->display.get_cdclk = fixed_450mhz_get_cdclk;
>  	else if (IS_GM45(dev_priv))
>  		dev_priv->display.get_cdclk = gm45_get_cdclk;
> diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
> index 68f2fb89ece3..bf4fd739b68c 100644
> --- a/drivers/gpu/drm/i915/intel_crt.c
> +++ b/drivers/gpu/drm/i915/intel_crt.c
> @@ -322,7 +322,7 @@ intel_crt_mode_valid(struct drm_connector *connector,
>  		 * DAC limit supposedly 355 MHz.
>  		 */
>  		max_clock = 270000;
> -	else if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv))
> +	else if (IS_GEN(dev_priv, 3) || IS_GEN(dev_priv, 4))
>  		max_clock = 400000;
>  	else
>  		max_clock = 350000;
> @@ -666,7 +666,7 @@ intel_crt_load_detect(struct intel_crt *crt, uint32_t pipe)
>  	/* Set the border color to purple. */
>  	I915_WRITE(bclrpat_reg, 0x500050);
>  
> -	if (!IS_GEN2(dev_priv)) {
> +	if (!IS_GEN(dev_priv, 2)) {
>  		uint32_t pipeconf = I915_READ(pipeconf_reg);
>  		I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER);
>  		POSTING_READ(pipeconf_reg);
> @@ -981,7 +981,7 @@ void intel_crt_init(struct drm_i915_private *dev_priv)
>  	else
>  		crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
>  
> -	if (IS_GEN2(dev_priv))
> +	if (IS_GEN(dev_priv, 2))
>  		connector->interlace_allowed = 0;
>  	else
>  		connector->interlace_allowed = 1;
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 1e56319334f3..332790279e1d 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -748,7 +748,7 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
>  	if (INTEL_GEN(dev_priv) >= 10) {
>  		for_each_pipe(dev_priv, pipe)
>  			info->num_scalers[pipe] = 2;
> -	} else if (IS_GEN9(dev_priv)) {
> +	} else if (IS_GEN(dev_priv, 9)) {
>  		info->num_scalers[PIPE_A] = 2;
>  		info->num_scalers[PIPE_B] = 2;
>  		info->num_scalers[PIPE_C] = 1;
> @@ -756,10 +756,10 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
>  
>  	BUILD_BUG_ON(I915_NUM_ENGINES > BITS_PER_TYPE(intel_ring_mask_t));
>  
> -	if (IS_GEN11(dev_priv))
> +	if (IS_GEN(dev_priv, 11))
>  		for_each_pipe(dev_priv, pipe)
>  			info->num_sprites[pipe] = 6;
> -	else if (IS_GEN10(dev_priv) || IS_GEMINILAKE(dev_priv))
> +	else if (IS_GEN(dev_priv, 10) || IS_GEMINILAKE(dev_priv))
>  		for_each_pipe(dev_priv, pipe)
>  			info->num_sprites[pipe] = 3;
>  	else if (IS_BROXTON(dev_priv)) {
> @@ -787,7 +787,7 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
>  		DRM_INFO("Display disabled (module parameter)\n");
>  		info->num_pipes = 0;
>  	} else if (HAS_DISPLAY(dev_priv) &&
> -		   (IS_GEN7(dev_priv) || IS_GEN8(dev_priv)) &&
> +		   (IS_GEN(dev_priv, 7) || IS_GEN(dev_priv, 8)) &&
>  		   HAS_PCH_SPLIT(dev_priv)) {
>  		u32 fuse_strap = I915_READ(FUSE_STRAP);
>  		u32 sfuse_strap = I915_READ(SFUSE_STRAP);
> @@ -811,7 +811,7 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
>  			DRM_INFO("PipeC fused off\n");
>  			info->num_pipes -= 1;
>  		}
> -	} else if (HAS_DISPLAY(dev_priv) && IS_GEN9(dev_priv)) {
> +	} else if (HAS_DISPLAY(dev_priv) && IS_GEN(dev_priv, 9)) {
>  		u32 dfsm = I915_READ(SKL_DFSM);
>  		u8 disabled_mask = 0;
>  		bool invalid;
> @@ -851,14 +851,14 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
>  		cherryview_sseu_info_init(dev_priv);
>  	else if (IS_BROADWELL(dev_priv))
>  		broadwell_sseu_info_init(dev_priv);
> -	else if (IS_GEN9(dev_priv))
> +	else if (IS_GEN(dev_priv, 9))
>  		gen9_sseu_info_init(dev_priv);
> -	else if (IS_GEN10(dev_priv))
> +	else if (IS_GEN(dev_priv, 10))
>  		gen10_sseu_info_init(dev_priv);
>  	else if (INTEL_GEN(dev_priv) >= 11)
>  		gen11_sseu_info_init(dev_priv);
>  
> -	if (IS_GEN6(dev_priv) && intel_vtd_active()) {
> +	if (IS_GEN(dev_priv, 6) && intel_vtd_active()) {
>  		DRM_INFO("Disabling ppGTT for VT-d support\n");
>  		info->ppgtt = INTEL_PPGTT_NONE;
>  	}
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 07c861884c70..07ddb06fec65 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -984,7 +984,7 @@ static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv,
>  	u32 line1, line2;
>  	u32 line_mask;
>  
> -	if (IS_GEN2(dev_priv))
> +	if (IS_GEN(dev_priv, 2))
>  		line_mask = DSL_LINEMASK_GEN2;
>  	else
>  		line_mask = DSL_LINEMASK_GEN3;
> @@ -1110,7 +1110,7 @@ static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
>  	u32 val;
>  
>  	/* ILK FDI PLL is always enabled */
> -	if (IS_GEN5(dev_priv))
> +	if (IS_GEN(dev_priv, 5))
>  		return;
>  
>  	/* On Haswell, DDI ports are responsible for the FDI PLL setup */
> @@ -1850,7 +1850,7 @@ static void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state)
>  
>  static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
>  {
> -	return IS_GEN2(dev_priv) ? 2048 : 4096;
> +	return IS_GEN(dev_priv, 2) ? 2048 : 4096;
>  }
>  
>  static unsigned int
> @@ -1863,7 +1863,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
>  	case DRM_FORMAT_MOD_LINEAR:
>  		return cpp;
>  	case I915_FORMAT_MOD_X_TILED:
> -		if (IS_GEN2(dev_priv))
> +		if (IS_GEN(dev_priv, 2))
>  			return 128;
>  		else
>  			return 512;
> @@ -1872,7 +1872,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
>  			return 128;
>  		/* fall through */
>  	case I915_FORMAT_MOD_Y_TILED:
> -		if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
> +		if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
>  			return 128;
>  		else
>  			return 512;
> @@ -3193,8 +3193,8 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
>  
>  	dspcntr = DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE;
>  
> -	if (IS_G4X(dev_priv) || IS_GEN5(dev_priv) ||
> -	    IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
> +	if (IS_G4X(dev_priv) || IS_GEN(dev_priv, 5) ||
> +	    IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
>  		dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
>  
>  	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> @@ -4120,7 +4120,7 @@ static void gen6_fdi_link_train(struct intel_crtc *crtc,
>  	temp = I915_READ(reg);
>  	temp &= ~FDI_LINK_TRAIN_NONE;
>  	temp |= FDI_LINK_TRAIN_PATTERN_2;
> -	if (IS_GEN6(dev_priv)) {
> +	if (IS_GEN(dev_priv, 6)) {
>  		temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
>  		/* SNB-B */
>  		temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
> @@ -4919,10 +4919,10 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
>  	/* range checks */
>  	if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
>  	    dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
> -	    (IS_GEN11(dev_priv) &&
> +	    (IS_GEN(dev_priv, 11) &&
>  	     (src_w > ICL_MAX_SRC_W || src_h > ICL_MAX_SRC_H ||
>  	      dst_w > ICL_MAX_DST_W || dst_h > ICL_MAX_DST_H)) ||
> -	    (!IS_GEN11(dev_priv) &&
> +	    (!IS_GEN(dev_priv, 11) &&
>  	     (src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
>  	      dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H)))	{
>  		DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
> @@ -5213,7 +5213,7 @@ intel_post_enable_primary(struct drm_crtc *crtc,
>  	 * FIXME: Need to fix the logic to work when we turn off all planes
>  	 * but leave the pipe running.
>  	 */
> -	if (IS_GEN2(dev_priv))
> +	if (IS_GEN(dev_priv, 2))
>  		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
>  
>  	/* Underruns don't always raise interrupts, so check manually. */
> @@ -5234,7 +5234,7 @@ intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
>  	 * Gen2 reports pipe underruns whenever all planes are disabled.
>  	 * So disable underrun reporting before all the planes get disabled.
>  	 */
> -	if (IS_GEN2(dev_priv))
> +	if (IS_GEN(dev_priv, 2))
>  		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
>  
>  	hsw_disable_ips(to_intel_crtc_state(crtc->state));
> @@ -5292,7 +5292,7 @@ static bool needs_nv12_wa(struct drm_i915_private *dev_priv,
>  		return false;
>  
>  	/* WA Display #0827: Gen9:all */
> -	if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv))
> +	if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv))
>  		return true;
>  
>  	return false;
> @@ -5365,7 +5365,7 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
>  		 * Gen2 reports pipe underruns whenever all planes are disabled.
>  		 * So disable underrun reporting before all the planes get disabled.
>  		 */
> -		if (IS_GEN2(dev_priv) && old_primary_state->visible &&
> +		if (IS_GEN(dev_priv, 2) && old_primary_state->visible &&
>  		    (modeset || !new_primary_state->base.visible))
>  			intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
>  	}
> @@ -6184,7 +6184,7 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
>  
>  	intel_crtc->active = true;
>  
> -	if (!IS_GEN2(dev_priv))
> +	if (!IS_GEN(dev_priv, 2))
>  		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
>  
>  	intel_encoders_pre_enable(crtc, pipe_config, old_state);
> @@ -6236,7 +6236,7 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
>  	 * On gen2 planes are double buffered but the pipe isn't, so we must
>  	 * wait for planes to fully turn off before disabling the pipe.
>  	 */
> -	if (IS_GEN2(dev_priv))
> +	if (IS_GEN(dev_priv, 2))
>  		intel_wait_for_vblank(dev_priv, pipe);
>  
>  	intel_encoders_disable(crtc, old_crtc_state, old_state);
> @@ -6261,7 +6261,7 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
>  
>  	intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
>  
> -	if (!IS_GEN2(dev_priv))
> +	if (!IS_GEN(dev_priv, 2))
>  		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
>  
>  	if (!dev_priv->display.initial_watermarks)
> @@ -6868,7 +6868,7 @@ static bool transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
>  	 * Strictly speaking some registers are available before
>  	 * gen7, but we only support DRRS on gen7+
>  	 */
> -	return IS_GEN7(dev_priv) || IS_CHERRYVIEW(dev_priv);
> +	return IS_GEN(dev_priv, 7) || IS_CHERRYVIEW(dev_priv);
>  }
>  
>  static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
> @@ -9005,7 +9005,7 @@ static void ironlake_get_pfit_config(struct intel_crtc *crtc,
>  		/* We currently do not free assignements of panel fitters on
>  		 * ivb/hsw (since we don't use the higher upscaling modes which
>  		 * differentiates them) so just WARN about this case for now. */
> -		if (IS_GEN7(dev_priv)) {
> +		if (IS_GEN(dev_priv, 7)) {
>  			WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
>  				PF_PIPE_SEL_IVB(crtc->pipe));
>  		}
> @@ -9995,7 +9995,7 @@ static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>  	u32 cntl = 0;
>  
> -	if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
> +	if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
>  		cntl |= MCURSOR_TRICKLE_FEED_DISABLE;
>  
>  	if (INTEL_GEN(dev_priv) <= 10) {
> @@ -10468,7 +10468,7 @@ static int i9xx_pll_refclk(struct drm_device *dev,
>  		return dev_priv->vbt.lvds_ssc_freq;
>  	else if (HAS_PCH_SPLIT(dev_priv))
>  		return 120000;
> -	else if (!IS_GEN2(dev_priv))
> +	else if (!IS_GEN(dev_priv, 2))
>  		return 96000;
>  	else
>  		return 48000;
> @@ -10501,7 +10501,7 @@ static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
>  		clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
>  	}
>  
> -	if (!IS_GEN2(dev_priv)) {
> +	if (!IS_GEN(dev_priv, 2)) {
>  		if (IS_PINEVIEW(dev_priv))
>  			clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
>  				DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
> @@ -10817,7 +10817,7 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat
>  	 * the w/a on all three platforms.
>  	 */
>  	if (plane->id == PLANE_SPRITE0 &&
> -	    (IS_GEN5(dev_priv) || IS_GEN6(dev_priv) ||
> +	    (IS_GEN(dev_priv, 5) || IS_GEN(dev_priv, 6) ||
>  	     IS_IVYBRIDGE(dev_priv)) &&
>  	    (turn_on || (!needs_scaling(old_plane_state) &&
>  			 needs_scaling(to_intel_plane_state(plane_state)))))
> @@ -12378,7 +12378,7 @@ static void update_scanline_offset(const struct intel_crtc_state *crtc_state)
>  	 * However if queried just before the start of vblank we'll get an
>  	 * answer that's slightly in the future.
>  	 */
> -	if (IS_GEN2(dev_priv)) {
> +	if (IS_GEN(dev_priv, 2)) {
>  		const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
>  		int vtotal;
>  
> @@ -13578,7 +13578,7 @@ void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
>  {
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  
> -	if (!IS_GEN2(dev_priv))
> +	if (!IS_GEN(dev_priv, 2))
>  		intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
>  
>  	if (crtc_state->has_pch_encoder) {
> @@ -14185,7 +14185,7 @@ static bool has_edp_a(struct drm_i915_private *dev_priv)
>  	if ((I915_READ(DP_A) & DP_DETECTED) == 0)
>  		return false;
>  
> -	if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
> +	if (IS_GEN(dev_priv, 5) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
>  		return false;
>  
>  	return true;
> @@ -14397,7 +14397,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
>  		}
>  
>  		vlv_dsi_init(dev_priv);
> -	} else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) {
> +	} else if (!IS_GEN(dev_priv, 2) && !IS_PINEVIEW(dev_priv)) {
>  		bool found = false;
>  
>  		if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
> @@ -14431,7 +14431,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
>  
>  		if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
>  			intel_dp_init(dev_priv, DP_D, PORT_D);
> -	} else if (IS_GEN2(dev_priv))
> +	} else if (IS_GEN(dev_priv, 2))
>  		intel_dvo_init(dev_priv);
>  
>  	if (SUPPORTS_TV(dev_priv))
> @@ -14629,7 +14629,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
>  		 * require the entire fb to accommodate that to avoid
>  		 * potential runtime errors at plane configuration time.
>  		 */
> -		if (IS_GEN9(dev_priv) && i == 0 && fb->width > 3840 &&
> +		if (IS_GEN(dev_priv, 9) && i == 0 && fb->width > 3840 &&
>  		    is_ccs_modifier(fb->modifier))
>  			stride_alignment *= 4;
>  
> @@ -14834,7 +14834,7 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
>  		dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
>  		dev_priv->display.crtc_enable = i9xx_crtc_enable;
>  		dev_priv->display.crtc_disable = i9xx_crtc_disable;
> -	} else if (!IS_GEN2(dev_priv)) {
> +	} else if (!IS_GEN(dev_priv, 2)) {
>  		dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
>  		dev_priv->display.get_initial_plane_config =
>  			i9xx_get_initial_plane_config;
> @@ -14850,9 +14850,9 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
>  		dev_priv->display.crtc_disable = i9xx_crtc_disable;
>  	}
>  
> -	if (IS_GEN5(dev_priv)) {
> +	if (IS_GEN(dev_priv, 5)) {
>  		dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
> -	} else if (IS_GEN6(dev_priv)) {
> +	} else if (IS_GEN(dev_priv, 6)) {
>  		dev_priv->display.fdi_link_train = gen6_fdi_link_train;
>  	} else if (IS_IVYBRIDGE(dev_priv)) {
>  		/* FIXME: detect B0+ stepping and use auto training */
> @@ -14984,12 +14984,12 @@ static void sanitize_watermarks(struct drm_device *dev)
>  
>  static void intel_update_fdi_pll_freq(struct drm_i915_private *dev_priv)
>  {
> -	if (IS_GEN5(dev_priv)) {
> +	if (IS_GEN(dev_priv, 5)) {
>  		u32 fdi_pll_clk =
>  			I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK;
>  
>  		dev_priv->fdi_pll_freq = (fdi_pll_clk + 2) * 10000;
> -	} else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
> +	} else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv)) {
>  		dev_priv->fdi_pll_freq = 270000;
>  	} else {
>  		return;
> @@ -15105,10 +15105,10 @@ int intel_modeset_init(struct drm_device *dev)
>  	}
>  
>  	/* maximum framebuffer dimensions */
> -	if (IS_GEN2(dev_priv)) {
> +	if (IS_GEN(dev_priv, 2)) {
>  		dev->mode_config.max_width = 2048;
>  		dev->mode_config.max_height = 2048;
> -	} else if (IS_GEN3(dev_priv)) {
> +	} else if (IS_GEN(dev_priv, 3)) {
>  		dev->mode_config.max_width = 4096;
>  		dev->mode_config.max_height = 4096;
>  	} else {
> @@ -15119,7 +15119,7 @@ int intel_modeset_init(struct drm_device *dev)
>  	if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
>  		dev->mode_config.cursor_width = IS_I845G(dev_priv) ? 64 : 512;
>  		dev->mode_config.cursor_height = 1023;
> -	} else if (IS_GEN2(dev_priv)) {
> +	} else if (IS_GEN(dev_priv, 2)) {
>  		dev->mode_config.cursor_width = 64;
>  		dev->mode_config.cursor_height = 64;
>  	} else {
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index de4219721cbc..2e0ccbfb5c2e 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -344,7 +344,7 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
>  	if (INTEL_GEN(dev_priv) >= 10) {
>  		source_rates = cnl_rates;
>  		size = ARRAY_SIZE(cnl_rates);
> -		if (IS_GEN10(dev_priv))
> +		if (IS_GEN(dev_priv, 10))
>  			max_rate = cnl_max_source_rate(intel_dp);
>  		else
>  			max_rate = icl_max_source_rate(intel_dp);
> @@ -1128,7 +1128,7 @@ static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
>  			to_i915(intel_dig_port->base.base.dev);
>  	uint32_t precharge, timeout;
>  
> -	if (IS_GEN6(dev_priv))
> +	if (IS_GEN(dev_priv, 6))
>  		precharge = 3;
>  	else
>  		precharge = 5;
> @@ -2585,7 +2585,7 @@ static void edp_panel_on(struct intel_dp *intel_dp)
>  
>  	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
>  	pp = ironlake_get_pp_control(intel_dp);
> -	if (IS_GEN5(dev_priv)) {
> +	if (IS_GEN(dev_priv, 5)) {
>  		/* ILK workaround: disable reset around power sequence */
>  		pp &= ~PANEL_POWER_RESET;
>  		I915_WRITE(pp_ctrl_reg, pp);
> @@ -2593,7 +2593,7 @@ static void edp_panel_on(struct intel_dp *intel_dp)
>  	}
>  
>  	pp |= PANEL_POWER_ON;
> -	if (!IS_GEN5(dev_priv))
> +	if (!IS_GEN(dev_priv, 5))
>  		pp |= PANEL_POWER_RESET;
>  
>  	I915_WRITE(pp_ctrl_reg, pp);
> @@ -2602,7 +2602,7 @@ static void edp_panel_on(struct intel_dp *intel_dp)
>  	wait_panel_on(intel_dp);
>  	intel_dp->last_power_on = jiffies;
>  
> -	if (IS_GEN5(dev_priv)) {
> +	if (IS_GEN(dev_priv, 5)) {
>  		pp |= PANEL_POWER_RESET; /* restore panel reset bit */
>  		I915_WRITE(pp_ctrl_reg, pp);
>  		POSTING_READ(pp_ctrl_reg);
> @@ -2831,7 +2831,7 @@ static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
>  	 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
>  	 * 2. Program DP PLL enable
>  	 */
> -	if (IS_GEN5(dev_priv))
> +	if (IS_GEN(dev_priv, 5))
>  		intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
>  
>  	intel_dp->DP |= DP_PLL_ENABLE;
> @@ -3849,7 +3849,7 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp)
>  	} else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
>  		signal_levels = ivb_cpu_edp_signal_levels(train_set);
>  		mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
> -	} else if (IS_GEN6(dev_priv) && port == PORT_A) {
> +	} else if (IS_GEN(dev_priv, 6) && port == PORT_A) {
>  		signal_levels = snb_cpu_edp_signal_levels(train_set);
>  		mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
>  	} else {
> @@ -5271,17 +5271,17 @@ bool intel_digital_port_connected(struct intel_encoder *encoder)
>  
>  	if (INTEL_GEN(dev_priv) >= 11)
>  		return icl_digital_port_connected(encoder);
> -	else if (IS_GEN10(dev_priv) || IS_GEN9_BC(dev_priv))
> +	else if (IS_GEN(dev_priv, 10) || IS_GEN9_BC(dev_priv))
>  		return spt_digital_port_connected(encoder);
>  	else if (IS_GEN9_LP(dev_priv))
>  		return bxt_digital_port_connected(encoder);
> -	else if (IS_GEN8(dev_priv))
> +	else if (IS_GEN(dev_priv, 8))
>  		return bdw_digital_port_connected(encoder);
> -	else if (IS_GEN7(dev_priv))
> +	else if (IS_GEN(dev_priv, 7))
>  		return ivb_digital_port_connected(encoder);
> -	else if (IS_GEN6(dev_priv))
> +	else if (IS_GEN(dev_priv, 6))
>  		return snb_digital_port_connected(encoder);
> -	else if (IS_GEN5(dev_priv))
> +	else if (IS_GEN(dev_priv, 5))
>  		return ilk_digital_port_connected(encoder);
>  
>  	MISSING_CASE(INTEL_GEN(dev_priv));
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index fe5e87b6e1af..8ff794db7881 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -438,7 +438,7 @@ void intel_engine_init_global_seqno(struct intel_engine_cs *engine, u32 seqno)
>  	 * the semaphore value, then when the seqno moves backwards all
>  	 * future waits will complete instantly (causing rendering corruption).
>  	 */
> -	if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
> +	if (IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7)) {
>  		I915_WRITE(RING_SYNC_0(engine->mmio_base), 0);
>  		I915_WRITE(RING_SYNC_1(engine->mmio_base), 0);
>  		if (HAS_VEBOX(dev_priv))
> @@ -774,7 +774,7 @@ u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv)
>  	u32 slice = fls(sseu->slice_mask);
>  	u32 subslice = fls(sseu->subslice_mask[slice]);
>  
> -	if (IS_GEN10(dev_priv))
> +	if (IS_GEN(dev_priv, 10))
>  		mcr_s_ss_select = GEN8_MCR_SLICE(slice) |
>  				  GEN8_MCR_SUBSLICE(subslice);
>  	else if (INTEL_GEN(dev_priv) >= 11)
> diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
> index b57e31fc0f1e..1d3ff026d1bc 100644
> --- a/drivers/gpu/drm/i915/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/intel_fbc.c
> @@ -84,7 +84,7 @@ static int intel_fbc_calculate_cfb_size(struct drm_i915_private *dev_priv,
>  	int lines;
>  
>  	intel_fbc_get_plane_source_size(cache, NULL, &lines);
> -	if (IS_GEN7(dev_priv))
> +	if (IS_GEN(dev_priv, 7))
>  		lines = min(lines, 2048);
>  	else if (INTEL_GEN(dev_priv) >= 8)
>  		lines = min(lines, 2560);
> @@ -127,7 +127,7 @@ static void i8xx_fbc_activate(struct drm_i915_private *dev_priv)
>  		cfb_pitch = params->fb.stride;
>  
>  	/* FBC_CTL wants 32B or 64B units */
> -	if (IS_GEN2(dev_priv))
> +	if (IS_GEN(dev_priv, 2))
>  		cfb_pitch = (cfb_pitch / 32) - 1;
>  	else
>  		cfb_pitch = (cfb_pitch / 64) - 1;
> @@ -136,7 +136,7 @@ static void i8xx_fbc_activate(struct drm_i915_private *dev_priv)
>  	for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
>  		I915_WRITE(FBC_TAG(i), 0);
>  
> -	if (IS_GEN4(dev_priv)) {
> +	if (IS_GEN(dev_priv, 4)) {
>  		u32 fbc_ctl2;
>  
>  		/* Set it up... */
> @@ -233,9 +233,9 @@ static void ilk_fbc_activate(struct drm_i915_private *dev_priv)
>  
>  	if (params->flags & PLANE_HAS_FENCE) {
>  		dpfc_ctl |= DPFC_CTL_FENCE_EN;
> -		if (IS_GEN5(dev_priv))
> +		if (IS_GEN(dev_priv, 5))
>  			dpfc_ctl |= params->vma->fence->id;
> -		if (IS_GEN6(dev_priv)) {
> +		if (IS_GEN(dev_priv, 6)) {
>  			I915_WRITE(SNB_DPFC_CTL_SA,
>  				   SNB_CPU_FENCE_ENABLE |
>  				   params->vma->fence->id);
> @@ -243,7 +243,7 @@ static void ilk_fbc_activate(struct drm_i915_private *dev_priv)
>  				   params->crtc.fence_y_offset);
>  		}
>  	} else {
> -		if (IS_GEN6(dev_priv)) {
> +		if (IS_GEN(dev_priv, 6)) {
>  			I915_WRITE(SNB_DPFC_CTL_SA, 0);
>  			I915_WRITE(DPFC_CPU_FENCE_OFFSET, 0);
>  		}
> @@ -282,7 +282,7 @@ static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
>  	int threshold = dev_priv->fbc.threshold;
>  
>  	/* Display WA #0529: skl, kbl, bxt. */
> -	if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv)) {
> +	if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv)) {
>  		u32 val = I915_READ(CHICKEN_MISC_4);
>  
>  		val &= ~(FBC_STRIDE_OVERRIDE | FBC_STRIDE_MASK);
> @@ -581,10 +581,10 @@ static bool stride_is_valid(struct drm_i915_private *dev_priv,
>  	if (stride < 512)
>  		return false;
>  
> -	if (IS_GEN2(dev_priv) || IS_GEN3(dev_priv))
> +	if (IS_GEN(dev_priv, 2) || IS_GEN(dev_priv, 3))
>  		return stride == 4096 || stride == 8192;
>  
> -	if (IS_GEN4(dev_priv) && !IS_G4X(dev_priv) && stride < 2048)
> +	if (IS_GEN(dev_priv, 4) && !IS_G4X(dev_priv) && stride < 2048)
>  		return false;
>  
>  	if (stride > 16384)
> @@ -603,7 +603,7 @@ static bool pixel_format_is_valid(struct drm_i915_private *dev_priv,
>  	case DRM_FORMAT_XRGB1555:
>  	case DRM_FORMAT_RGB565:
>  		/* 16bpp not supported on gen2 */
> -		if (IS_GEN2(dev_priv))
> +		if (IS_GEN(dev_priv, 2))
>  			return false;
>  		/* WaFbcOnly1to1Ratio:ctg */
>  		if (IS_G4X(dev_priv))
> @@ -842,7 +842,7 @@ static void intel_fbc_get_reg_params(struct intel_crtc *crtc,
>  
>  	params->cfb_size = intel_fbc_calculate_cfb_size(dev_priv, cache);
>  
> -	if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv))
> +	if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv))
>  		params->gen9_wa_cfb_stride = DIV_ROUND_UP(cache->plane.src_w,
>  						32 * fbc->threshold) * 8;
>  }
> diff --git a/drivers/gpu/drm/i915/intel_fifo_underrun.c b/drivers/gpu/drm/i915/intel_fifo_underrun.c
> index 77c123cc8817..ff2743ccbece 100644
> --- a/drivers/gpu/drm/i915/intel_fifo_underrun.c
> +++ b/drivers/gpu/drm/i915/intel_fifo_underrun.c
> @@ -260,9 +260,9 @@ static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
>  
>  	if (HAS_GMCH_DISPLAY(dev_priv))
>  		i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old);
> -	else if (IS_GEN5(dev_priv) || IS_GEN6(dev_priv))
> +	else if (IS_GEN(dev_priv, 5) || IS_GEN(dev_priv, 6))
>  		ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
> -	else if (IS_GEN7(dev_priv))
> +	else if (IS_GEN(dev_priv, 7))
>  		ivybridge_set_fifo_underrun_reporting(dev, pipe, enable, old);
>  	else if (INTEL_GEN(dev_priv) >= 8)
>  		broadwell_set_fifo_underrun_reporting(dev, pipe, enable);
> @@ -423,7 +423,7 @@ void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv)
>  
>  		if (HAS_GMCH_DISPLAY(dev_priv))
>  			i9xx_check_fifo_underruns(crtc);
> -		else if (IS_GEN7(dev_priv))
> +		else if (IS_GEN(dev_priv, 7))
>  			ivybridge_check_fifo_underruns(crtc);
>  	}
>  
> diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c b/drivers/gpu/drm/i915/intel_guc_fw.c
> index a67144ee5ceb..4b437e05e2cd 100644
> --- a/drivers/gpu/drm/i915/intel_guc_fw.c
> +++ b/drivers/gpu/drm/i915/intel_guc_fw.c
> @@ -115,7 +115,7 @@ static void guc_prepare_xfer(struct intel_guc *guc)
>  	else
>  		I915_WRITE(GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
>  
> -	if (IS_GEN9(dev_priv)) {
> +	if (IS_GEN(dev_priv, 9)) {
>  		/* DOP Clock Gating Enable for GuC clocks */
>  		I915_WRITE(GEN7_MISCCPCTL, (GEN8_DOP_CLOCK_GATE_GUC_ENABLE |
>  					    I915_READ(GEN7_MISCCPCTL)));
> diff --git a/drivers/gpu/drm/i915/intel_hangcheck.c b/drivers/gpu/drm/i915/intel_hangcheck.c
> index 41921a843d42..495fa145f37f 100644
> --- a/drivers/gpu/drm/i915/intel_hangcheck.c
> +++ b/drivers/gpu/drm/i915/intel_hangcheck.c
> @@ -236,7 +236,7 @@ engine_stuck(struct intel_engine_cs *engine, u64 acthd)
>  	if (ha != ENGINE_DEAD)
>  		return ha;
>  
> -	if (IS_GEN2(dev_priv))
> +	if (IS_GEN(dev_priv, 2))
>  		return ENGINE_DEAD;
>  
>  	/* Is the chip hanging on a WAIT_FOR_EVENT?
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index d7fa301b5ec7..9cb8fb8f1982 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -2002,7 +2002,7 @@ static int gen8_emit_flush_render(struct i915_request *request,
>  		 * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
>  		 * pipe control.
>  		 */
> -		if (IS_GEN9(request->i915))
> +		if (IS_GEN(request->i915, 9))
>  			vf_flush_wa = true;
>  
>  		/* WaForGAMHang:kbl */
> @@ -2357,7 +2357,7 @@ make_rpcs(struct drm_i915_private *dev_priv)
>  	 * subslices are enabled, or a count between one and four on the first
>  	 * slice.
>  	 */
> -	if (IS_GEN11(dev_priv) && slices == 1 && subslices >= 4) {
> +	if (IS_GEN(dev_priv, 11) && slices == 1 && subslices >= 4) {
>  		GEM_BUG_ON(subslices & 1);
>  
>  		subslice_pg = false;
> diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
> index e6c5d985ea0a..b85e195f7c8a 100644
> --- a/drivers/gpu/drm/i915/intel_lvds.c
> +++ b/drivers/gpu/drm/i915/intel_lvds.c
> @@ -279,7 +279,7 @@ static void intel_pre_enable_lvds(struct intel_encoder *encoder,
>  	 * special lvds dither control bit on pch-split platforms, dithering is
>  	 * only controlled through the PIPECONF reg.
>  	 */
> -	if (IS_GEN4(dev_priv)) {
> +	if (IS_GEN(dev_priv, 4)) {
>  		/*
>  		 * Bspec wording suggests that LVDS port dithering only exists
>  		 * for 18bpp panels.
> @@ -919,7 +919,7 @@ void intel_lvds_init(struct drm_i915_private *dev_priv)
>  	intel_encoder->cloneable = 0;
>  	if (HAS_PCH_SPLIT(dev_priv))
>  		intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
> -	else if (IS_GEN4(dev_priv))
> +	else if (IS_GEN(dev_priv, 4))
>  		intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
>  	else
>  		intel_encoder->crtc_mask = (1 << 1);
> diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
> index 77e9871a8c9a..e976c5ce5479 100644
> --- a/drivers/gpu/drm/i915/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/intel_mocs.c
> @@ -193,7 +193,7 @@ static bool get_mocs_settings(struct drm_i915_private *dev_priv,
>  	}
>  
>  	/* WaDisableSkipCaching:skl,bxt,kbl,glk */
> -	if (IS_GEN9(dev_priv)) {
> +	if (IS_GEN(dev_priv, 9)) {
>  		int i;
>  
>  		for (i = 0; i < table->size; i++)
> diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c
> index 20ea7c99d13a..c153be043078 100644
> --- a/drivers/gpu/drm/i915/intel_overlay.c
> +++ b/drivers/gpu/drm/i915/intel_overlay.c
> @@ -541,7 +541,7 @@ static u32 calc_swidthsw(struct drm_i915_private *dev_priv, u32 offset, u32 widt
>  {
>  	u32 sw;
>  
> -	if (IS_GEN2(dev_priv))
> +	if (IS_GEN(dev_priv, 2))
>  		sw = ALIGN((offset & 31) + width, 32);
>  	else
>  		sw = ALIGN((offset & 63) + width, 64);
> @@ -778,7 +778,7 @@ static int intel_overlay_do_put_image(struct intel_overlay *overlay,
>  		u32 oconfig;
>  
>  		oconfig = OCONF_CC_OUT_8BIT;
> -		if (IS_GEN4(dev_priv))
> +		if (IS_GEN(dev_priv, 4))
>  			oconfig |= OCONF_CSC_MODE_BT709;
>  		oconfig |= pipe == 0 ?
>  			OCONF_PIPE_A : OCONF_PIPE_B;
> @@ -1012,7 +1012,7 @@ static int check_overlay_src(struct drm_i915_private *dev_priv,
>  
>  	if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask)
>  		return -EINVAL;
> -	if (IS_GEN4(dev_priv) && rec->stride_Y < 512)
> +	if (IS_GEN(dev_priv, 4) && rec->stride_Y < 512)
>  		return -EINVAL;
>  
>  	tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ?
> @@ -1246,7 +1246,7 @@ int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
>  		attrs->contrast   = overlay->contrast;
>  		attrs->saturation = overlay->saturation;
>  
> -		if (!IS_GEN2(dev_priv)) {
> +		if (!IS_GEN(dev_priv, 2)) {
>  			attrs->gamma0 = I915_READ(OGAMC0);
>  			attrs->gamma1 = I915_READ(OGAMC1);
>  			attrs->gamma2 = I915_READ(OGAMC2);
> @@ -1270,7 +1270,7 @@ int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
>  		update_reg_attrs(overlay, overlay->regs);
>  
>  		if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) {
> -			if (IS_GEN2(dev_priv))
> +			if (IS_GEN(dev_priv, 2))
>  				goto out_unlock;
>  
>  			if (overlay->active) {
> diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
> index e6cd7b55c018..ee3e0842d542 100644
> --- a/drivers/gpu/drm/i915/intel_panel.c
> +++ b/drivers/gpu/drm/i915/intel_panel.c
> @@ -563,7 +563,7 @@ static void i9xx_set_backlight(const struct drm_connector_state *conn_state, u32
>  		pci_write_config_byte(dev_priv->drm.pdev, LBPC, lbpc);
>  	}
>  
> -	if (IS_GEN4(dev_priv)) {
> +	if (IS_GEN(dev_priv, 4)) {
>  		mask = BACKLIGHT_DUTY_CYCLE_MASK;
>  	} else {
>  		level <<= 1;
> @@ -929,7 +929,7 @@ static void i9xx_enable_backlight(const struct intel_crtc_state *crtc_state,
>  	 * 855gm only, but checking for gen2 is safe, as 855gm is the only gen2
>  	 * that has backlight.
>  	 */
> -	if (IS_GEN2(dev_priv))
> +	if (IS_GEN(dev_priv, 2))
>  		I915_WRITE(BLC_HIST_CTL, BLM_HISTOGRAM_ENABLE);
>  }
>  
> @@ -1557,7 +1557,7 @@ static int i9xx_setup_backlight(struct intel_connector *connector, enum pipe unu
>  
>  	ctl = I915_READ(BLC_PWM_CTL);
>  
> -	if (IS_GEN2(dev_priv) || IS_I915GM(dev_priv) || IS_I945GM(dev_priv))
> +	if (IS_GEN(dev_priv, 2) || IS_I915GM(dev_priv) || IS_I945GM(dev_priv))
>  		panel->backlight.combination_mode = ctl & BLM_LEGACY_MODE;
>  
>  	if (IS_PINEVIEW(dev_priv))
> @@ -1886,7 +1886,7 @@ intel_panel_init_backlight_funcs(struct intel_panel *panel)
>  			panel->backlight.get = vlv_get_backlight;
>  			panel->backlight.hz_to_pwm = vlv_hz_to_pwm;
>  		}
> -	} else if (IS_GEN4(dev_priv)) {
> +	} else if (IS_GEN(dev_priv, 4)) {
>  		panel->backlight.setup = i965_setup_backlight;
>  		panel->backlight.enable = i965_enable_backlight;
>  		panel->backlight.disable = i965_disable_backlight;
> diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c b/drivers/gpu/drm/i915/intel_pipe_crc.c
> index f3c9010e332a..9e870caf8104 100644
> --- a/drivers/gpu/drm/i915/intel_pipe_crc.c
> +++ b/drivers/gpu/drm/i915/intel_pipe_crc.c
> @@ -427,13 +427,13 @@ static int get_new_crc_ctl_reg(struct drm_i915_private *dev_priv,
>  			       enum intel_pipe_crc_source *source, u32 *val,
>  			       bool set_wa)
>  {
> -	if (IS_GEN2(dev_priv))
> +	if (IS_GEN(dev_priv, 2))
>  		return i8xx_pipe_crc_ctl_reg(source, val);
>  	else if (INTEL_GEN(dev_priv) < 5)
>  		return i9xx_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
>  	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>  		return vlv_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
> -	else if (IS_GEN5(dev_priv) || IS_GEN6(dev_priv))
> +	else if (IS_GEN(dev_priv, 5) || IS_GEN(dev_priv, 6))
>  		return ilk_pipe_crc_ctl_reg(source, val);
>  	else
>  		return ivb_pipe_crc_ctl_reg(dev_priv, pipe, source, val, set_wa);
> @@ -544,13 +544,13 @@ static int
>  intel_is_valid_crc_source(struct drm_i915_private *dev_priv,
>  			  const enum intel_pipe_crc_source source)
>  {
> -	if (IS_GEN2(dev_priv))
> +	if (IS_GEN(dev_priv, 2))
>  		return i8xx_crc_source_valid(dev_priv, source);
>  	else if (INTEL_GEN(dev_priv) < 5)
>  		return i9xx_crc_source_valid(dev_priv, source);
>  	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>  		return vlv_crc_source_valid(dev_priv, source);
> -	else if (IS_GEN5(dev_priv) || IS_GEN6(dev_priv))
> +	else if (IS_GEN(dev_priv, 5) || IS_GEN(dev_priv, 6))
>  		return ilk_crc_source_valid(dev_priv, source);
>  	else
>  		return ivb_crc_source_valid(dev_priv, source);
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index a26b4eddda25..9d6becec4200 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -2273,7 +2273,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
>  
>  	if (IS_I945GM(dev_priv))
>  		wm_info = &i945_wm_info;
> -	else if (!IS_GEN2(dev_priv))
> +	else if (!IS_GEN(dev_priv, 2))
>  		wm_info = &i915_wm_info;
>  	else
>  		wm_info = &i830_a_wm_info;
> @@ -2287,7 +2287,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
>  			crtc->base.primary->state->fb;
>  		int cpp;
>  
> -		if (IS_GEN2(dev_priv))
> +		if (IS_GEN(dev_priv, 2))
>  			cpp = 4;
>  		else
>  			cpp = fb->format->cpp[0];
> @@ -2302,7 +2302,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
>  			planea_wm = wm_info->max_wm;
>  	}
>  
> -	if (IS_GEN2(dev_priv))
> +	if (IS_GEN(dev_priv, 2))
>  		wm_info = &i830_bc_wm_info;
>  
>  	fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_B);
> @@ -2314,7 +2314,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
>  			crtc->base.primary->state->fb;
>  		int cpp;
>  
> -		if (IS_GEN2(dev_priv))
> +		if (IS_GEN(dev_priv, 2))
>  			cpp = 4;
>  		else
>  			cpp = fb->format->cpp[0];
> @@ -2926,7 +2926,7 @@ static void intel_fixup_spr_wm_latency(struct drm_i915_private *dev_priv,
>  				       uint16_t wm[5])
>  {
>  	/* ILK sprite LP0 latency is 1300 ns */
> -	if (IS_GEN5(dev_priv))
> +	if (IS_GEN(dev_priv, 5))
>  		wm[0] = 13;
>  }
>  
> @@ -2934,7 +2934,7 @@ static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv,
>  				       uint16_t wm[5])
>  {
>  	/* ILK cursor LP0 latency is 1300 ns */
> -	if (IS_GEN5(dev_priv))
> +	if (IS_GEN(dev_priv, 5))
>  		wm[0] = 13;
>  }
>  
> @@ -3061,7 +3061,7 @@ static void ilk_setup_wm_latency(struct drm_i915_private *dev_priv)
>  	intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
>  	intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
>  
> -	if (IS_GEN6(dev_priv)) {
> +	if (IS_GEN(dev_priv, 6)) {
>  		snb_wm_latency_quirk(dev_priv);
>  		snb_wm_lp3_irq_quirk(dev_priv);
>  	}
> @@ -3318,7 +3318,7 @@ static void ilk_wm_merge(struct drm_device *dev,
>  	 * What we should check here is whether FBC can be
>  	 * enabled sometime later.
>  	 */
> -	if (IS_GEN5(dev_priv) && !merged->fbc_wm_enabled &&
> +	if (IS_GEN(dev_priv, 5) && !merged->fbc_wm_enabled &&
>  	    intel_fbc_is_active(dev_priv)) {
>  		for (level = 2; level <= max_level; level++) {
>  			struct intel_wm_level *wm = &merged->wm[level];
> @@ -3756,9 +3756,9 @@ bool intel_can_enable_sagv(struct drm_atomic_state *state)
>  	if (!intel_has_sagv(dev_priv))
>  		return false;
>  
> -	if (IS_GEN9(dev_priv))
> +	if (IS_GEN(dev_priv, 9))
>  		sagv_block_time_us = 30;
> -	else if (IS_GEN10(dev_priv))
> +	else if (IS_GEN(dev_priv, 10))
>  		sagv_block_time_us = 20;
>  	else
>  		sagv_block_time_us = 10;
> @@ -4702,7 +4702,7 @@ skl_compute_plane_wm_params(const struct intel_crtc_state *cstate,
>  
>  		wp->plane_blocks_per_line = div_fixed16(interm_pbpl,
>  							wp->y_min_scanlines);
> -	} else if (wp->x_tiled && IS_GEN9(dev_priv)) {
> +	} else if (wp->x_tiled && IS_GEN(dev_priv, 9)) {
>  		interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line,
>  					   wp->dbuf_block_size);
>  		wp->plane_blocks_per_line = u32_to_fixed16(interm_pbpl);
> @@ -4768,13 +4768,13 @@ static int skl_compute_plane_wm(const struct intel_crtc_state *cstate,
>  			selected_result = method2;
>  		} else if (ddb_allocation >=
>  			 fixed16_to_u32_round_up(wp->plane_blocks_per_line)) {
> -			if (IS_GEN9(dev_priv) &&
> +			if (IS_GEN(dev_priv, 9) &&
>  			    !IS_GEMINILAKE(dev_priv))
>  				selected_result = min_fixed16(method1, method2);
>  			else
>  				selected_result = method2;
>  		} else if (latency >= wp->linetime_us) {
> -			if (IS_GEN9(dev_priv) &&
> +			if (IS_GEN(dev_priv, 9) &&
>  			    !IS_GEMINILAKE(dev_priv))
>  				selected_result = min_fixed16(method1, method2);
>  			else
> @@ -7049,7 +7049,7 @@ static void gen9_enable_rps(struct drm_i915_private *dev_priv)
>  	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
>  
>  	/* Program defaults and thresholds for RPS */
> -	if (IS_GEN9(dev_priv))
> +	if (IS_GEN(dev_priv, 9))
>  		I915_WRITE(GEN6_RC_VIDEO_FREQ,
>  			GEN9_FREQUENCY(dev_priv->gt_pm.rps.rp1_freq));
>  
> @@ -7285,9 +7285,9 @@ static void gen6_enable_rc6(struct drm_i915_private *dev_priv)
>  
>  	rc6vids = 0;
>  	ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
> -	if (IS_GEN6(dev_priv) && ret) {
> +	if (IS_GEN(dev_priv, 6) && ret) {
>  		DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
> -	} else if (IS_GEN6(dev_priv) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
> +	} else if (IS_GEN(dev_priv, 6) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
>  		DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
>  			  GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
>  		rc6vids &= 0xffff00;
> @@ -7987,7 +7987,7 @@ unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
>  {
>  	unsigned long val;
>  
> -	if (!IS_GEN5(dev_priv))
> +	if (!IS_GEN(dev_priv, 5))
>  		return 0;
>  
>  	spin_lock_irq(&mchdev_lock);
> @@ -8071,7 +8071,7 @@ static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
>  
>  void i915_update_gfx_val(struct drm_i915_private *dev_priv)
>  {
> -	if (!IS_GEN5(dev_priv))
> +	if (!IS_GEN(dev_priv, 5))
>  		return;
>  
>  	spin_lock_irq(&mchdev_lock);
> @@ -8122,7 +8122,7 @@ unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
>  {
>  	unsigned long val;
>  
> -	if (!IS_GEN5(dev_priv))
> +	if (!IS_GEN(dev_priv, 5))
>  		return 0;
>  
>  	spin_lock_irq(&mchdev_lock);
> @@ -8410,7 +8410,7 @@ void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
>  			      intel_freq_opcode(dev_priv, 450));
>  
>  	/* After setting max-softlimit, find the overclock max freq */
> -	if (IS_GEN6(dev_priv) ||
> +	if (IS_GEN(dev_priv, 6) ||
>  	    IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
>  		u32 params = 0;
>  
> @@ -9480,9 +9480,9 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
>  		dev_priv->display.init_clock_gating = ivb_init_clock_gating;
>  	else if (IS_VALLEYVIEW(dev_priv))
>  		dev_priv->display.init_clock_gating = vlv_init_clock_gating;
> -	else if (IS_GEN6(dev_priv))
> +	else if (IS_GEN(dev_priv, 6))
>  		dev_priv->display.init_clock_gating = gen6_init_clock_gating;
> -	else if (IS_GEN5(dev_priv))
> +	else if (IS_GEN(dev_priv, 5))
>  		dev_priv->display.init_clock_gating = ilk_init_clock_gating;
>  	else if (IS_G4X(dev_priv))
>  		dev_priv->display.init_clock_gating = g4x_init_clock_gating;
> @@ -9490,11 +9490,11 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
>  		dev_priv->display.init_clock_gating = i965gm_init_clock_gating;
>  	else if (IS_I965G(dev_priv))
>  		dev_priv->display.init_clock_gating = i965g_init_clock_gating;
> -	else if (IS_GEN3(dev_priv))
> +	else if (IS_GEN(dev_priv, 3))
>  		dev_priv->display.init_clock_gating = gen3_init_clock_gating;
>  	else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
>  		dev_priv->display.init_clock_gating = i85x_init_clock_gating;
> -	else if (IS_GEN2(dev_priv))
> +	else if (IS_GEN(dev_priv, 2))
>  		dev_priv->display.init_clock_gating = i830_init_clock_gating;
>  	else {
>  		MISSING_CASE(INTEL_DEVID(dev_priv));
> @@ -9508,7 +9508,7 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
>  	/* For cxsr */
>  	if (IS_PINEVIEW(dev_priv))
>  		i915_pineview_get_mem_freq(dev_priv);
> -	else if (IS_GEN5(dev_priv))
> +	else if (IS_GEN(dev_priv, 5))
>  		i915_ironlake_get_mem_freq(dev_priv);
>  
>  	/* For FIFO watermark updates */
> @@ -9520,9 +9520,9 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
>  	} else if (HAS_PCH_SPLIT(dev_priv)) {
>  		ilk_setup_wm_latency(dev_priv);
>  
> -		if ((IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[1] &&
> +		if ((IS_GEN(dev_priv, 5) && dev_priv->wm.pri_latency[1] &&
>  		     dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
> -		    (!IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[0] &&
> +		    (!IS_GEN(dev_priv, 5) && dev_priv->wm.pri_latency[0] &&
>  		     dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
>  			dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
>  			dev_priv->display.compute_intermediate_wm =
> @@ -9563,12 +9563,12 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
>  			dev_priv->display.update_wm = NULL;
>  		} else
>  			dev_priv->display.update_wm = pineview_update_wm;
> -	} else if (IS_GEN4(dev_priv)) {
> +	} else if (IS_GEN(dev_priv, 4)) {
>  		dev_priv->display.update_wm = i965_update_wm;
> -	} else if (IS_GEN3(dev_priv)) {
> +	} else if (IS_GEN(dev_priv, 3)) {
>  		dev_priv->display.update_wm = i9xx_update_wm;
>  		dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
> -	} else if (IS_GEN2(dev_priv)) {
> +	} else if (IS_GEN(dev_priv, 2)) {
>  		if (INTEL_INFO(dev_priv)->num_pipes == 1) {
>  			dev_priv->display.update_wm = i845_update_wm;
>  			dev_priv->display.get_fifo_size = i845_get_fifo_size;
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 4c4dd1c310ce..dce39f06b682 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -552,7 +552,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
>  	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
>  		psr_max_h = 4096;
>  		psr_max_v = 2304;
> -	} else if (IS_GEN9(dev_priv)) {
> +	} else if (IS_GEN(dev_priv, 9)) {
>  		psr_max_h = 3640;
>  		psr_max_v = 2304;
>  	}
> @@ -686,7 +686,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
>  	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
>  		hsw_psr_setup_aux(intel_dp);
>  
> -	if (dev_priv->psr.psr2_enabled && (IS_GEN9(dev_priv) &&
> +	if (dev_priv->psr.psr2_enabled && (IS_GEN(dev_priv, 9) &&
>  					   !IS_GEMINILAKE(dev_priv))) {
>  		i915_reg_t reg = gen9_chicken_trans_reg(dev_priv,
>  							cpu_transcoder);
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index a205cc9e60cc..bb8c90284385 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -124,7 +124,7 @@ gen4_render_ring_flush(struct i915_request *rq, u32 mode)
>  	cmd = MI_FLUSH;
>  	if (mode & EMIT_INVALIDATE) {
>  		cmd |= MI_EXE_FLUSH;
> -		if (IS_G4X(rq->i915) || IS_GEN5(rq->i915))
> +		if (IS_G4X(rq->i915) || IS_GEN(rq->i915, 5))
>  			cmd |= MI_INVALIDATE_ISP;
>  	}
>  
> @@ -392,7 +392,7 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
>  	/* The ring status page addresses are no longer next to the rest of
>  	 * the ring registers as of gen7.
>  	 */
> -	if (IS_GEN7(dev_priv)) {
> +	if (IS_GEN(dev_priv, 7)) {
>  		switch (engine->id) {
>  		/*
>  		 * No more rings exist on Gen7. Default case is only to shut up
> @@ -413,7 +413,7 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
>  			mmio = VEBOX_HWS_PGA_GEN7;
>  			break;
>  		}
> -	} else if (IS_GEN6(dev_priv)) {
> +	} else if (IS_GEN(dev_priv, 6)) {
>  		mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
>  	} else {
>  		mmio = RING_HWS_PGA(engine->mmio_base);
> @@ -684,17 +684,17 @@ static int init_render_ring(struct intel_engine_cs *engine)
>  
>  	/* Required for the hardware to program scanline values for waiting */
>  	/* WaEnableFlushTlbInvalidationMode:snb */
> -	if (IS_GEN6(dev_priv))
> +	if (IS_GEN(dev_priv, 6))
>  		I915_WRITE(GFX_MODE,
>  			   _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
>  
>  	/* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
> -	if (IS_GEN7(dev_priv))
> +	if (IS_GEN(dev_priv, 7))
>  		I915_WRITE(GFX_MODE_GEN7,
>  			   _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
>  			   _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
>  
> -	if (IS_GEN6(dev_priv)) {
> +	if (IS_GEN(dev_priv, 6)) {
>  		/* From the Sandybridge PRM, volume 1 part 3, page 24:
>  		 * "If this bit is set, STCunit will have LRA as replacement
>  		 *  policy. [...] This bit must be reset.  LRA replacement
> @@ -1573,7 +1573,7 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags)
>  	enum intel_engine_id id;
>  	const int num_rings =
>  		/* Use an extended w/a on gen7 if signalling from other rings */
> -		(HAS_LEGACY_SEMAPHORES(i915) && IS_GEN7(i915)) ?
> +		(HAS_LEGACY_SEMAPHORES(i915) && IS_GEN(i915, 7)) ?
>  		INTEL_INFO(i915)->num_rings - 1 :
>  		0;
>  	bool force_restore = false;
> @@ -1588,7 +1588,7 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags)
>  		flags |= MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN;
>  
>  	len = 4;
> -	if (IS_GEN7(i915))
> +	if (IS_GEN(i915, 7))
>  		len += 2 + (num_rings ? 4*num_rings + 6 : 0);
>  	if (flags & MI_FORCE_RESTORE) {
>  		GEM_BUG_ON(flags & MI_RESTORE_INHIBIT);
> @@ -1602,7 +1602,7 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags)
>  		return PTR_ERR(cs);
>  
>  	/* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
> -	if (IS_GEN7(i915)) {
> +	if (IS_GEN(i915, 7)) {
>  		*cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
>  		if (num_rings) {
>  			struct intel_engine_cs *signaller;
> @@ -1649,7 +1649,7 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags)
>  	 */
>  	*cs++ = MI_NOOP;
>  
> -	if (IS_GEN7(i915)) {
> +	if (IS_GEN(i915, 7)) {
>  		if (num_rings) {
>  			struct intel_engine_cs *signaller;
>  			i915_reg_t last_reg = {}; /* keep gcc quiet */
> @@ -2272,9 +2272,9 @@ int intel_init_render_ring_buffer(struct intel_engine_cs *engine)
>  	if (INTEL_GEN(dev_priv) >= 6) {
>  		engine->init_context = intel_rcs_ctx_init;
>  		engine->emit_flush = gen7_render_ring_flush;
> -		if (IS_GEN6(dev_priv))
> +		if (IS_GEN(dev_priv, 6))
>  			engine->emit_flush = gen6_render_ring_flush;
> -	} else if (IS_GEN5(dev_priv)) {
> +	} else if (IS_GEN(dev_priv, 5)) {
>  		engine->emit_flush = gen4_render_ring_flush;
>  	} else {
>  		if (INTEL_GEN(dev_priv) < 4)
> @@ -2304,13 +2304,13 @@ int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine)
>  
>  	if (INTEL_GEN(dev_priv) >= 6) {
>  		/* gen6 bsd needs a special wa for tail updates */
> -		if (IS_GEN6(dev_priv))
> +		if (IS_GEN(dev_priv, 6))
>  			engine->set_default_submission = gen6_bsd_set_default_submission;
>  		engine->emit_flush = gen6_bsd_ring_flush;
>  		engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;
>  	} else {
>  		engine->emit_flush = bsd_ring_flush;
> -		if (IS_GEN5(dev_priv))
> +		if (IS_GEN(dev_priv, 5))
>  			engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
>  		else
>  			engine->irq_enable_mask = I915_BSD_USER_INTERRUPT;
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index 72edaa7ff411..1ae74e579386 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -94,11 +94,11 @@ hangcheck_action_to_str(const enum intel_engine_hangcheck_action a)
>  #define I915_MAX_SUBSLICES 8
>  
>  #define instdone_slice_mask(dev_priv__) \
> -	(IS_GEN7(dev_priv__) ? \
> +	(IS_GEN(dev_priv__, 7) ? \
>  	 1 : INTEL_INFO(dev_priv__)->sseu.slice_mask)
>  
>  #define instdone_subslice_mask(dev_priv__) \
> -	(IS_GEN7(dev_priv__) ? \
> +	(IS_GEN(dev_priv__, 7) ? \
>  	 1 : INTEL_INFO(dev_priv__)->sseu.subslice_mask[0])
>  
>  #define for_each_instdone_slice_subslice(dev_priv__, slice__, subslice__) \
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 4350a5270423..9e9501f82f06 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -509,7 +509,7 @@ static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
>  	 * BIOS's own request bits, which are forced-on for these power wells
>  	 * when exiting DC5/6.
>  	 */
> -	if (IS_GEN9(dev_priv) && !IS_GEN9_LP(dev_priv) &&
> +	if (IS_GEN(dev_priv, 9) && !IS_GEN9_LP(dev_priv) &&
>  	    (id == SKL_DISP_PW_1 || id == SKL_DISP_PW_MISC_IO))
>  		val |= I915_READ(regs->bios);
>  
> @@ -3058,7 +3058,7 @@ static uint32_t get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
>  		 * suspend/resume, so allow it unconditionally.
>  		 */
>  		mask = DC_STATE_EN_DC9;
> -	} else if (IS_GEN10(dev_priv) || IS_GEN9_BC(dev_priv)) {
> +	} else if (IS_GEN(dev_priv, 10) || IS_GEN9_BC(dev_priv)) {
>  		max_dc = 2;
>  		mask = 0;
>  	} else if (IS_GEN9_LP(dev_priv)) {
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index d2e003d8f3db..f70d2c607902 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -1087,7 +1087,7 @@ static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,
>  
>  	dvscntr = DVS_ENABLE | DVS_GAMMA_ENABLE;
>  
> -	if (IS_GEN6(dev_priv))
> +	if (IS_GEN(dev_priv, 6))
>  		dvscntr |= DVS_TRICKLE_FEED_DISABLE;
>  
>  	switch (fb->format->format) {
> @@ -1983,7 +1983,7 @@ static bool skl_plane_has_planar(struct drm_i915_private *dev_priv,
>  	if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
>  		return false;
>  
> -	if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv) && pipe == PIPE_C)
> +	if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv) && pipe == PIPE_C)
>  		return false;
>  
>  	if (plane_id != PLANE_PRIMARY && plane_id != PLANE_SPRITE0)
> @@ -2163,7 +2163,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
>  		plane->check_plane = g4x_sprite_check;
>  
>  		modifiers = i9xx_plane_format_modifiers;
> -		if (IS_GEN6(dev_priv)) {
> +		if (IS_GEN(dev_priv, 6)) {
>  			formats = snb_plane_formats;
>  			num_formats = ARRAY_SIZE(snb_plane_formats);
>  
> diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
> index b34c318b238d..447b1de77cc7 100644
> --- a/drivers/gpu/drm/i915/intel_uc.c
> +++ b/drivers/gpu/drm/i915/intel_uc.c
> @@ -354,7 +354,7 @@ int intel_uc_init_hw(struct drm_i915_private *i915)
>  
>  	/* WaEnableuKernelHeaderValidFix:skl */
>  	/* WaEnableGuCBootHashCheckNotSet:skl,bxt,kbl */
> -	if (IS_GEN9(i915))
> +	if (IS_GEN(i915, 9))
>  		attempts = 3;
>  	else
>  		attempts = 1;
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index 631b4165fe00..c6eb053a8fad 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -528,7 +528,7 @@ check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
>  	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>  		ret |= vlv_check_for_unclaimed_mmio(dev_priv);
>  
> -	if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv))
> +	if (IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7))
>  		ret |= gen6_check_for_fifo_debug(dev_priv);
>  
>  	return ret;
> @@ -556,7 +556,7 @@ static void __intel_uncore_early_sanitize(struct drm_i915_private *dev_priv,
>  		dev_priv->uncore.funcs.force_wake_get(dev_priv,
>  						      restore_forcewake);
>  
> -		if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv))
> +		if (IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7))
>  			dev_priv->uncore.fifo_count =
>  				fifo_free_entries(dev_priv);
>  		spin_unlock_irq(&dev_priv->uncore.lock);
> @@ -1398,7 +1398,7 @@ static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv)
>  	if (INTEL_GEN(dev_priv) <= 5 || intel_vgpu_active(dev_priv))
>  		return;
>  
> -	if (IS_GEN6(dev_priv)) {
> +	if (IS_GEN(dev_priv, 6)) {
>  		dev_priv->uncore.fw_reset = 0;
>  		dev_priv->uncore.fw_set = FORCEWAKE_KERNEL;
>  		dev_priv->uncore.fw_clear = 0;
> @@ -1437,7 +1437,7 @@ static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv)
>  				       FORCEWAKE_MEDIA_VEBOX_GEN11(i),
>  				       FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(i));
>  		}
> -	} else if (IS_GEN10(dev_priv) || IS_GEN9(dev_priv)) {
> +	} else if (IS_GEN(dev_priv, 10) || IS_GEN(dev_priv, 9)) {
>  		dev_priv->uncore.funcs.force_wake_get =
>  			fw_domains_get_with_fallback;
>  		dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
> @@ -1503,7 +1503,7 @@ static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv)
>  			fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
>  				       FORCEWAKE, FORCEWAKE_ACK);
>  		}
> -	} else if (IS_GEN6(dev_priv)) {
> +	} else if (IS_GEN(dev_priv, 6)) {
>  		dev_priv->uncore.funcs.force_wake_get =
>  			fw_domains_get_with_thread_status;
>  		dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
> @@ -1570,7 +1570,7 @@ void intel_uncore_init(struct drm_i915_private *dev_priv)
>  	if (IS_GEN_RANGE(dev_priv, 2, 4) || intel_vgpu_active(dev_priv)) {
>  		ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen2);
>  		ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen2);
> -	} else if (IS_GEN5(dev_priv)) {
> +	} else if (IS_GEN(dev_priv, 5)) {
>  		ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen5);
>  		ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen5);
>  	} else if (IS_GEN_RANGE(dev_priv, 6, 7)) {
> @@ -1582,7 +1582,7 @@ void intel_uncore_init(struct drm_i915_private *dev_priv)
>  		} else {
>  			ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen6);
>  		}
> -	} else if (IS_GEN8(dev_priv)) {
> +	} else if (IS_GEN(dev_priv, 8)) {
>  		if (IS_CHERRYVIEW(dev_priv)) {
>  			ASSIGN_FW_DOMAINS_TABLE(__chv_fw_ranges);
>  			ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, fwtable);
> @@ -2173,7 +2173,7 @@ static reset_func intel_get_gpu_reset(struct drm_i915_private *dev_priv)
>  		return gen8_reset_engines;
>  	else if (INTEL_GEN(dev_priv) >= 6)
>  		return gen6_reset_engines;
> -	else if (IS_GEN5(dev_priv))
> +	else if (IS_GEN(dev_priv, 5))
>  		return ironlake_do_reset;
>  	else if (IS_G4X(dev_priv))
>  		return g4x_do_reset;
> @@ -2341,7 +2341,7 @@ intel_uncore_forcewake_for_write(struct drm_i915_private *dev_priv,
>  		fw_domains = __gen11_fwtable_reg_write_fw_domains(offset);
>  	} else if (HAS_FWTABLE(dev_priv) && !IS_VALLEYVIEW(dev_priv)) {
>  		fw_domains = __fwtable_reg_write_fw_domains(offset);
> -	} else if (IS_GEN8(dev_priv)) {
> +	} else if (IS_GEN(dev_priv, 8)) {
>  		fw_domains = __gen8_reg_write_fw_domains(offset);
>  	} else if (IS_GEN_RANGE(dev_priv, 6, 7)) {
>  		fw_domains = FORCEWAKE_RENDER;
> diff --git a/drivers/gpu/drm/i915/intel_wopcm.c b/drivers/gpu/drm/i915/intel_wopcm.c
> index 92cb82dd0c07..630c887682e8 100644
> --- a/drivers/gpu/drm/i915/intel_wopcm.c
> +++ b/drivers/gpu/drm/i915/intel_wopcm.c
> @@ -130,11 +130,11 @@ static inline int check_hw_restriction(struct drm_i915_private *i915,
>  {
>  	int err = 0;
>  
> -	if (IS_GEN9(i915))
> +	if (IS_GEN(i915, 9))
>  		err = gen9_check_dword_gap(guc_wopcm_base, guc_wopcm_size);
>  
>  	if (!err &&
> -	    (IS_GEN9(i915) || IS_CNL_REVID(i915, CNL_REVID_A0, CNL_REVID_A0)))
> +	    (IS_GEN(i915, 9) || IS_CNL_REVID(i915, CNL_REVID_A0, CNL_REVID_A0)))
>  		err = gen9_check_huc_fw_fits(guc_wopcm_size, huc_fw_size);
>  
>  	return err;
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index a4ab78bdcbbf..71d17250f1ff 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -1184,7 +1184,7 @@ static void rcs_engine_wa_init(struct intel_engine_cs *engine)
>  			    PMFLUSHDONE_LNEBLK);
>  	}
>  
> -	if (IS_GEN9(i915) || IS_CANNONLAKE(i915)) {
> +	if (IS_GEN(i915, 9) || IS_CANNONLAKE(i915)) {
>  		/* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,cnl */
>  		wa_masked_en(wal,
>  			     GEN7_FF_SLICE_CS_CHICKEN1,
> @@ -1205,7 +1205,7 @@ static void rcs_engine_wa_init(struct intel_engine_cs *engine)
>  			     GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE);
>  	}
>  
> -	if (IS_GEN9(i915)) {
> +	if (IS_GEN(i915, 9)) {
>  		/* WaContextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk,cfl */
>  		wa_masked_en(wal,
>  			     GEN9_CSFE_CHICKEN1_RCS,

-- 
Jani Nikula, Intel Open Source Graphics Center
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