On Thu, 2018-11-29 at 18:25 -0800, José Roberto de Souza wrote: > Selective updates have a default granularity requirements as stated > by eDP spec Needs reference to the location in the spec. > , so check if HW can match those requirements before > enable PSR2. typo: enabling* > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@xxxxxxxxx> > Cc: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx> > Signed-off-by: José Roberto de Souza <jose.souza@xxxxxxxxx> > --- > drivers/gpu/drm/i915/intel_psr.c | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_psr.c > b/drivers/gpu/drm/i915/intel_psr.c > index c4a8f476eea9..282ff1bc68a7 100644 > --- a/drivers/gpu/drm/i915/intel_psr.c > +++ b/drivers/gpu/drm/i915/intel_psr.c > @@ -539,6 +539,18 @@ static bool intel_psr2_config_valid(struct > intel_dp *intel_dp, > return false; > } > > + /* HW will always send full lines in SU blocks, so X will s/X/starting X coordinate > + * always be 0 and we only need to check the width to validate > + * horizontal granularity. > + * About vertical granularity HW works by SU blocks starting > + * at each 4 lines with height of 4 lines, what eDP states > + * that sink should support. How about rewriting this as - "HW sends SU blocks of size four scan lines, which means the starting X coordinate and Y granularity requirements will always be met. We only need to validate the SU block width is a multiple of 4."? > + */ > + if (crtc_hdisplay % 4) { > + DRM_DEBUG_KMS("PSR2 not enabled, default SU granularity > not match\n"); "PSR2 not enabled, hdisplay(%d) not multiple of 4\n" With nits addressed, Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@xxxxxxxxx> > + return false; > + } > + > return true; > } > _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx