On Mon, Nov 26, 2018 at 04:37:04PM -0800, José Roberto de Souza wrote: > eDP spec states 2 different bits to enable sink to trigger a > interruption when there is a CRC mismatch. > DP_PSR_CRC_VERIFICATION is for PSR only and > DP_PSR_IRQ_HPD_WITH_CRC_ERRORS is for PSR2 only. > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@xxxxxxxxx> > Cc: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx> > Signed-off-by: José Roberto de Souza <jose.souza@xxxxxxxxx> > --- > drivers/gpu/drm/i915/intel_psr.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c > index 888e348cc1b4..607c3ec41679 100644 > --- a/drivers/gpu/drm/i915/intel_psr.c > +++ b/drivers/gpu/drm/i915/intel_psr.c > @@ -390,7 +390,7 @@ static void intel_psr_enable_sink(struct intel_dp *intel_dp) > if (dev_priv->psr.psr2_enabled) { > drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, > DP_ALPM_ENABLE); > - dpcd_val |= DP_PSR_ENABLE_PSR2; > + dpcd_val |= DP_PSR_ENABLE_PSR2 | DP_PSR_IRQ_HPD_WITH_CRC_ERRORS; good catch! Reviewed-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx> > } else { > if (dev_priv->psr.link_standby) > dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE; > -- > 2.19.2 > _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx