== Series Details == Series: series starting with [CI,v13,01/17] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state (rev3) URL : https://patchwork.freedesktop.org/series/53184/ State : success == Summary == CI Bug Log - changes from CI_DRM_5224 -> Patchwork_10963 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/53184/revisions/3/mbox/ Known issues ------------ Here are the changes found in Patchwork_10963 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a: - fi-byt-clapper: PASS -> FAIL [fdo#107362] #### Possible fixes #### * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence: - fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191 [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362 Participating hosts (50 -> 44) ------------------------------ Missing (6): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 Build changes ------------- * Linux: CI_DRM_5224 -> Patchwork_10963 CI_DRM_5224: 67ee0d0da79f5b32636d496fd2127da1eecf6262 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4736: 285ebfb3b7adc56586031afa5150c4e5ad40c229 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10963: bbc5b58c45f5879b861b2c8b01493a0bc958170a @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == bbc5b58c45f5 drm/i915/fec: Disable FEC state. fd072dec2471 i915/dp/fec: Configure the Forward Error Correction bits. f8545a54cbcb drm/i915/fec: Set FEC_READY in FEC_CONFIGURATION 7c08c67d8ce9 i915/dp/fec: Add fec_enable to the crtc state. 8f9d717516c7 drm/i915/dsc: Enable and disable appropriate power wells for VDSC 0c808e718014 drm/i915/dp: Disable DSC in source by disabling DSS CTL bits d2c1b3c51630 drm/i915/dp: Configure Display stream splitter registers during DSC enable 924582574b2f drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes 030d1fd500a0 drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs 51aa0ec34c42 drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling d9ac811835a4 drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI b4cbbbfeb28a drm/i915/dp: Enable/Disable DSC in DP Sink e6dd78c8b893 drm/i915/dsc: Compute Rate Control parameters for DSC 4578253d135c drm/i915/dsc: Define & Compute VESA DSC params ce2f079b691f drm/i915/dp: Do not enable PSR2 if DSC is enabled f4c722992aee drm/i915/dp: Compute DSC pipe config in atomic check cf74ed403002 drm/i915/dp: Add DSC params and DSC config to intel_crtc_state == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10963/ _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
