== Series Details == Series: series starting with [CI,v13,01/17] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state (rev3) URL : https://patchwork.freedesktop.org/series/53184/ State : warning == Summary == $ dim checkpatch origin/drm-tip cf74ed403002 drm/i915/dp: Add DSC params and DSC config to intel_crtc_state -:49: CHECK:BOOL_MEMBER: Avoid using bool structure members because of possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384 #49: FILE: drivers/gpu/drm/i915/intel_drv.h:948: + bool compression_enable; -:50: CHECK:BOOL_MEMBER: Avoid using bool structure members because of possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384 #50: FILE: drivers/gpu/drm/i915/intel_drv.h:949: + bool dsc_split; total: 0 errors, 0 warnings, 2 checks, 22 lines checked f4c722992aee drm/i915/dp: Compute DSC pipe config in atomic check ce2f079b691f drm/i915/dp: Do not enable PSR2 if DSC is enabled 4578253d135c drm/i915/dsc: Define & Compute VESA DSC params -:68: WARNING:BAD_SIGN_OFF: Non-standard signature: Co-developed-by: #68: Co-developed-by: Manasi Navare <manasi.d.navare@xxxxxxxxx> -:119: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #119: new file mode 100644 total: 0 errors, 2 warnings, 0 checks, 488 lines checked e6dd78c8b893 drm/i915/dsc: Compute Rate Control parameters for DSC b4cbbbfeb28a drm/i915/dp: Enable/Disable DSC in DP Sink d9ac811835a4 drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI 51aa0ec34c42 drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling -:391: WARNING:LONG_LINE: line over 100 characters #391: FILE: drivers/gpu/drm/i915/intel_vdsc.c:897: + rc_range_params_dword[i / 2] |= (u32)(((vdsc_cfg->rc_range_params[i].range_bpg_offset << total: 0 errors, 1 warnings, 0 checks, 426 lines checked 030d1fd500a0 drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs 924582574b2f drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes d2c1b3c51630 drm/i915/dp: Configure Display stream splitter registers during DSC enable 0c808e718014 drm/i915/dp: Disable DSC in source by disabling DSS CTL bits 8f9d717516c7 drm/i915/dsc: Enable and disable appropriate power wells for VDSC 7c08c67d8ce9 i915/dp/fec: Add fec_enable to the crtc state. -:126: CHECK:BOOL_MEMBER: Avoid using bool structure members because of possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384 #126: FILE: drivers/gpu/drm/i915/intel_drv.h:956: + bool fec_enable; total: 0 errors, 0 warnings, 1 checks, 65 lines checked f8545a54cbcb drm/i915/fec: Set FEC_READY in FEC_CONFIGURATION fd072dec2471 i915/dp/fec: Configure the Forward Error Correction bits. bbc5b58c45f5 drm/i915/fec: Disable FEC state. _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
