== Series Details == Series: series starting with [CI,v13,01/17] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state (rev2) URL : https://patchwork.freedesktop.org/series/53184/ State : success == Summary == CI Bug Log - changes from CI_DRM_5217 -> Patchwork_10939 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/53184/revisions/2/mbox/ Known issues ------------ Here are the changes found in Patchwork_10939 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@i915_selftest@live_contexts: - fi-bsw-kefka: PASS -> DMESG-FAIL [fdo#108626] / [fdo#108656] * igt@kms_frontbuffer_tracking@basic: - fi-byt-clapper: PASS -> FAIL [fdo#103167] * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence: - fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362] [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191 [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362 [fdo#108626]: https://bugs.freedesktop.org/show_bug.cgi?id=108626 [fdo#108656]: https://bugs.freedesktop.org/show_bug.cgi?id=108656 Participating hosts (49 -> 42) ------------------------------ Missing (7): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-j1900 fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 Build changes ------------- * Linux: CI_DRM_5217 -> Patchwork_10939 CI_DRM_5217: 3b8acd938b1edc326fb69d377cbceca8791df177 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4735: b05c028ccdb6ac8e8d8499a041bb14dfe358ee26 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10939: c878df13f9c00451f7281d105e0f2246cd65748c @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == c878df13f9c0 drm/i915/fec: Disable FEC state. 303f000edcd4 i915/dp/fec: Configure the Forward Error Correction bits. 2cb9fde528c3 drm/i915/fec: Set FEC_READY in FEC_CONFIGURATION 9211bdb6b64b i915/dp/fec: Add fec_enable to the crtc state. 2f4fb87c9b59 drm/i915/dsc: Enable and disable appropriate power wells for VDSC 1cfac339f7ea drm/i915/dp: Disable DSC in source by disabling DSS CTL bits ca153c0dbe0a drm/i915/dp: Configure Display stream splitter registers during DSC enable ad3fbff47ade drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes 909a40d71447 drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs f078f264482d drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling 0541a790e095 drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI 5a207b28b067 drm/i915/dp: Enable/Disable DSC in DP Sink f0efd1a5bded drm/i915/dsc: Compute Rate Control parameters for DSC 682f70ba2e90 drm/i915/dsc: Define & Compute VESA DSC params 7e99dcca72b9 drm/i915/dp: Do not enable PSR2 if DSC is enabled 3251c57ea8f7 drm/i915/dp: Compute DSC pipe config in atomic check 6cc046b0e53f drm/i915/dp: Add DSC params and DSC config to intel_crtc_state == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10939/ _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
