On Wed, Nov 14, 2018 at 11:07:16PM +0200, Ville Syrjala wrote: > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > Here's the remainder of the skl+ ddb/wm programming series. I tried to > split up the ugly monster patch into a few chunks, and I tossed in > a few extra nuggets on top. I also tried to improve the commit > messages a bit based on the previous review feedback. > > Entire series available here: > git://github.com/vsyrjala/linux.git skl_plane_ddb_wm_update_3 > > Ville Syrjälä (13): > drm/i915: Reorganize plane register writes to make them more atomic > drm/i915: Move single buffered plane register writes to the end > drm/i915: Introduce crtc_state->update_planes bitmask > drm/i915: Pass the new crtc_state to ->disable_plane() > drm/i915: Fix latency==0 handling for level 0 watermark on skl+ > drm/i915: Remove some useless zeroing on skl+ wm calculations > drm/i915: Pass the entire skl_plane_wm to skl_compute_transition_wm() > drm/i915: Clean up skl+ vs. icl+ watermark computation > drm/i915: Don't pass dev_priv around so much > drm/i915: Move ddb/wm programming into plane update/disable hooks on > skl+ > drm/i915: Commit skl+ planes in an order that avoids ddb overlaps > drm/i915: Rename the confusing 'plane_id' to 'color_plane' > drm/i915: Pass the plane to icl_program_input_csc_coeff() Entire series pushed to dinq. Thanks for the reviews everyone. -- Ville Syrjälä Intel _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
