Imre Deak <imre.deak@xxxxxxxxx> writes:
> On Fri, Nov 09, 2018 at 04:09:23PM +0200, Mika Kuoppala wrote:
>> Register DBUF_CTL_S2 is read and it's value is not used. As
>> there is no explanation why we should prime the hardware with
>> read, remove it as spurious.
>>
>> Fixes: aa9664ffe863 ("drm/i915/icl: Enable 2nd DBuf slice only when needed")
>> Cc: Mahesh Kumar <mahesh1.kumar@xxxxxxxxx>
>> Cc: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
>> Signed-off-by: Mika Kuoppala <mika.kuoppala@xxxxxxxxxxxxxxx>
>
> Reviewed-by: Imre Deak <imre.deak@xxxxxxxxx>
Pushed, thanks for review.
-Mika
>
>> ---
>> drivers/gpu/drm/i915/intel_runtime_pm.c | 4 +---
>> 1 file changed, 1 insertion(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
>> index f945db6ea420..770de2632530 100644
>> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
>> @@ -3236,8 +3236,7 @@ static u8 intel_dbuf_max_slices(struct drm_i915_private *dev_priv)
>> void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
>> u8 req_slices)
>> {
>> - u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices;
>> - u32 val;
>> + const u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices;
>> bool ret;
>>
>> if (req_slices > intel_dbuf_max_slices(dev_priv)) {
>> @@ -3248,7 +3247,6 @@ void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
>> if (req_slices == hw_enabled_slices || req_slices == 0)
>> return;
>>
>> - val = I915_READ(DBUF_CTL_S2);
>> if (req_slices > hw_enabled_slices)
>> ret = intel_dbuf_slice_set(dev_priv, DBUF_CTL_S2, true);
>> else
>> --
>> 2.17.1
>>
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