implemented context submission pvmmio optimizaiton with GVTg.
GVTg to read context submission data (elsp_data) from the shared_page
directly without trap cost to improve guest GPU peformrnace.
v0: RFC
v1: rebase
v2: rebase
v3: report pv context submission cap and handle VGT_G2V_ELSP_SUBMIT
g2v pv notification.
Cc: Zhenyu Wang <zhenyuw@xxxxxxxxxxxxxxx>
Cc: Zhi Wang <zhi.a.wang@xxxxxxxxx>
Cc: Min He <min.he@xxxxxxxxx>
Cc: Fei Jiang <fei.jiang@xxxxxxxxx>
Cc: Zhipeng Gong <zhipeng.gong@xxxxxxxxx>
Cc: Hang Yuan <hang.yuan@xxxxxxxxx>
Cc: Zhiyuan Lv <zhiyuan.lv@xxxxxxxxx>
Signed-off-by: Xiaolin Zhang <xiaolin.zhang@xxxxxxxxx>
---
drivers/gpu/drm/i915/gvt/gvt.h | 4 ++++
drivers/gpu/drm/i915/gvt/handlers.c | 39 ++++++++++++++++++++++++++++++++++++-
drivers/gpu/drm/i915/gvt/vgpu.c | 2 ++
3 files changed, 44 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h
index e013962..c8bd1f3 100644
--- a/drivers/gpu/drm/i915/gvt/gvt.h
+++ b/drivers/gpu/drm/i915/gvt/gvt.h
@@ -55,6 +55,10 @@
#define _vgtif_reg(x) \
(VGT_PVINFO_PAGE + offsetof(struct vgt_if, x))
+#define VGPU_PVMMIO(vgpu, level) \
+ ((vgpu_vreg_t(vgpu, vgtif_reg(pvmmio_caps)) & level) \
+ && vgpu->shared_page_enabled)
+
enum {
INTEL_GVT_HYPERVISOR_XEN = 0,
INTEL_GVT_HYPERVISOR_KVM,
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 16ef41b..1659bd1 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -1180,12 +1180,46 @@ static int pvinfo_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
return 0;
}
+static int intel_vgpu_g2v_pv_elsp_submit(struct intel_vgpu *vgpu)
+{
+ int ring_id;
+ struct intel_vgpu_execlist *execlist;
+ u32 elsp_data[4 * I915_NUM_ENGINES];
+ u32 elsp_data_off;
+ u32 ring_id_off;
+ int ret = -EINVAL;
+
+ if (!VGPU_PVMMIO(vgpu, PVMMIO_ELSP_SUBMIT))
+ return ret;
+
+ ring_id_off = offsetof(struct gvt_shared_page, ring_id);
+ if (intel_gvt_read_shared_page(vgpu, ring_id_off, &ring_id, 4))
+ return ret;
+
+ if (WARN_ON(ring_id < 0 || ring_id >= I915_NUM_ENGINES))
+ return ret;
+
+ elsp_data_off = offsetof(struct gvt_shared_page, elsp_data);
+ if (intel_gvt_read_shared_page(vgpu, elsp_data_off, &elsp_data,
+ 16 * I915_NUM_ENGINES))
+ return ret;
+
+ execlist = &vgpu->submission.execlist[ring_id];
+ execlist->elsp_dwords.data[3] = elsp_data[ring_id * 4 + 2];
+ execlist->elsp_dwords.data[2] = elsp_data[ring_id * 4 + 3];
+ execlist->elsp_dwords.data[1] = elsp_data[ring_id * 4 + 0];
+ execlist->elsp_dwords.data[0] = elsp_data[ring_id * 4 + 1];
+
+ return intel_vgpu_submit_execlist(vgpu, ring_id);
+}
+
static int handle_g2v_notification(struct intel_vgpu *vgpu, int notification)
{
intel_gvt_gtt_type_t root_entry_type = GTT_TYPE_PPGTT_ROOT_L4_ENTRY;
struct intel_vgpu_mm *mm;
u64 *pdps;
unsigned long gfn;
+ int ret = 0;
pdps = (u64 *)&vgpu_vreg64_t(vgpu, vgtif_reg(pdp[0]));
@@ -1204,6 +1238,9 @@ static int handle_g2v_notification(struct intel_vgpu *vgpu, int notification)
if (intel_gvt_hypervisor_is_valid_gfn(vgpu, gfn))
vgpu->shared_page_enabled = true;
break;
+ case VGT_G2V_ELSP_SUBMIT:
+ ret = intel_vgpu_g2v_pv_elsp_submit(vgpu);
+ break;
case VGT_G2V_EXECLIST_CONTEXT_CREATE:
case VGT_G2V_EXECLIST_CONTEXT_DESTROY:
case 1: /* Remove this in guest driver. */
@@ -1211,7 +1248,7 @@ static int handle_g2v_notification(struct intel_vgpu *vgpu, int notification)
default:
gvt_vgpu_err("Invalid PV notification %d\n", notification);
}
- return 0;
+ return ret;
}
static int send_display_ready_uevent(struct intel_vgpu *vgpu, int ready)
diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c
index 40aaae8..f98b591 100644
--- a/drivers/gpu/drm/i915/gvt/vgpu.c
+++ b/drivers/gpu/drm/i915/gvt/vgpu.c
@@ -49,6 +49,8 @@ void populate_pvinfo_page(struct intel_vgpu *vgpu)
vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HUGE_GTT;
vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_PVMMIO;
+ vgpu_vreg_t(vgpu, vgtif_reg(pvmmio_caps)) = PVMMIO_ELSP_SUBMIT;
+
vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base)) =
vgpu_aperture_gmadr_base(vgpu);
vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.mappable_gmadr.size)) =
--
2.7.4
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