Quoting Mika Kuoppala (2018-11-08 12:13:42) > Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> writes: > > > Quoting Mika Kuoppala (2018-11-08 12:00:39) > >> Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> writes: > >> > + /* > >> > + * Make sure the context image is complete before we submit it to HW. > >> > + * > >> > + * Ostensibly, writes (including the WCB) should be flushed prior to > >> > + * an uncached write such as our mmio register access, the empirical > >> > + * evidence (esp. on Braswell) suggests that the WC write into memory > >> > + * may not be visible to the HW prior to the completion of the UC > >> > + * register write and that we may begin execution from the context > >> > + * before its image is complete leading to invalid PD chasing. > >> > + */ > >> > + wmb(); > >> > >> Let's put it into use and gather more evidence. > >> > >> Reviewed-by: Mika Kuoppala <mika.kuoppala@xxxxxxxxxxxxxxx> > > > > Aye. Sure about r-b? I'm quite happy to take an a-b since we're just > > postulating to gather evidence. > > Agreed that a-b is more accurate. r-b would indicate I know what the > heck is going on there under the hood. And pushed (this patch) to see if the next few months do quieten down. -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
