== Series Details == Series: series starting with [CI,01/19] drm/dsc: Define Display Stream Compression PPS infoframe URL : https://patchwork.freedesktop.org/series/51997/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5083 -> Patchwork_10721 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/51997/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_10721 that come from known issues: === IGT changes === ==== Issues hit ==== igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a: fi-byt-clapper: PASS -> FAIL (fdo#107362) ==== Possible fixes ==== igt@gem_exec_suspend@basic-s4-devices: fi-blb-e6850: INCOMPLETE (fdo#107718) -> PASS igt@kms_flip@basic-flip-vs-dpms: fi-skl-6700hq: DMESG-WARN (fdo#105998) -> PASS igt@kms_frontbuffer_tracking@basic: fi-byt-clapper: FAIL (fdo#103167) -> PASS ==== Warnings ==== igt@drv_selftest@live_contexts: fi-icl-u2: INCOMPLETE (fdo#108315) -> DMESG-FAIL (fdo#108569) fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#105998 https://bugs.freedesktop.org/show_bug.cgi?id=105998 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718 fdo#108315 https://bugs.freedesktop.org/show_bug.cgi?id=108315 fdo#108569 https://bugs.freedesktop.org/show_bug.cgi?id=108569 == Participating hosts (50 -> 45) == Missing (5): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 == Build changes == * Linux: CI_DRM_5083 -> Patchwork_10721 CI_DRM_5083: a4e9f377a9b50521b5a07c544c97f67e3338f2c3 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4706: 5421c73a7db3cfaa85ab24325fe6e898cbb27fb3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10721: 64bb1ef628e8d7a30c1114e92be96158053bdd8d @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 64bb1ef628e8 drm/i915/dsc: Add Per connector debugfs node for DSC support/enable 9e778cbe005f drm/i915/dsc: Enable and disable appropriate power wells for VDSC 2a5b79ad1d98 drm/i915/dp: Disable DSC in source by disabling DSS CTL bits a92c77c255c1 drm/i915/dp: Configure Display stream splitter registers during DSC enable 60aae01038ed drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes 093a1a6e72a0 drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs 55228524d5aa drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling 3ff059cd1079 drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI 6d3d7696244f drm/i915/dp: Enable/Disable DSC in DP Sink d30d485fbaa5 drm/i915/dsc: Compute Rate Control parameters for DSC a11590e2c032 drm/i915/dsc: Define & Compute VESA DSC params 7f3efca7e47a drm/i915/dp: Do not enable PSR2 if DSC is enabled 476f87616dbe drm/i915/dp: Compute DSC pipe config in atomic check d16ba85051ec drm/i915/dp: Add DSC params and DSC config to intel_crtc_state 16ed1feab6af drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants 2fdfc3121810 drm/dsc: Add helpers for DSC picture parameter set infoframes 9e8cbea7c63a drm/dsc: Define Rate Control values that do not change over configurations c5a2fc29ad7f drm/dsc: Define VESA Display Stream Compression Capabilities e904fd188f2c drm/dsc: Define Display Stream Compression PPS infoframe == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10721/issues.html _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
