Hi 2012/6/28 Eugeni Dodonov <eugeni.dodonov at intel.com>: > This is required for a stable FDI connection. > > Signed-off-by: Eugeni Dodonov <eugeni.dodonov at intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 3 +++ > drivers/gpu/drm/i915/intel_ddi.c | 10 ++++++++++ > 2 files changed, 13 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 5b0c5f6..284965b 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -3849,6 +3849,9 @@ > #define _FDI_RXA_TUSIZE2 0xf0038 > #define _FDI_RXB_TUSIZE1 0xf1030 > #define _FDI_RXB_TUSIZE2 0xf1038 > +#define FDI_RX_TP1_TO_TP2_48 (10<<20) > +#define FDI_RX_TP1_TO_TP2_64 (11<<20) Isn't this supposed to be (2 << 20) and (3 << 20)? > +#define FDI_RX_FDI_DELAY_90 (0x90<<0) > #define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC) > #define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1) > #define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2) > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c > index effb263..1c76d20 100644 > --- a/drivers/gpu/drm/i915/intel_ddi.c > +++ b/drivers/gpu/drm/i915/intel_ddi.c > @@ -170,6 +170,16 @@ void hsw_fdi_link_train(struct drm_crtc *crtc) > > udelay(600); > > + /* We need to program FDI_RX_MISC with the default TP1 to TP2 > + * values before enabling the receiver, and configure the delay > + * for the FDI timing generator to 90h. > + */ > + reg = FDI_RX_MISC(pipe); > + temp = I915_READ(reg); > + temp |= FDI_RX_TP1_TO_TP2_48 | > + FDI_RX_FDI_DELAY_90; Shouldn't we mask bits 27:26, 25:24, 21:20 and 12:0 first? > + I915_WRITE(reg, temp); > + > /* Enable CPU FDI Receiver with auto-training */ > reg = FDI_RX_CTL(pipe); > I915_WRITE(reg, > -- > 1.7.11.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Paulo Zanoni
